| Message ID | 20231001103433.3187-3-jszhang@kernel.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | riscv: errata: thead: use riscv_nonstd_cache_ops for CMO | expand |
On Sun, Oct 1, 2023 at 6:46 PM Jisheng Zhang <jszhang@kernel.org> wrote: > > T-HEAD CPUs such as C906/C910/C920 support phy address based CMO, use > them so that we don't need to convert to virt address. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > arch/riscv/errata/thead/errata.c | 18 ++++++------------ > 1 file changed, 6 insertions(+), 12 deletions(-) > > diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c > index 3fefeb1b456e..632557f36b19 100644 > --- a/arch/riscv/errata/thead/errata.c > +++ b/arch/riscv/errata/thead/errata.c > @@ -58,9 +58,9 @@ static bool errata_probe_pbmt(unsigned int stage, > * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > * 0000000 11001 00000 000 00000 0001011 > */ > -#define THEAD_inval_A0 ".long 0x0265000b" > -#define THEAD_clean_A0 ".long 0x0255000b" > -#define THEAD_flush_A0 ".long 0x0275000b" > +#define THEAD_inval_A0 ".long 0x02a5000b" > +#define THEAD_clean_A0 ".long 0x0295000b" > +#define THEAD_flush_A0 ".long 0x02b5000b" > #define THEAD_SYNC_S ".long 0x0190000b" > > #define THEAD_CMO_OP(_op, _start, _size, _cachesize) \ > @@ -79,23 +79,17 @@ asm volatile("mv a0, %1\n\t" \ > > static void thead_errata_cache_inv(phys_addr_t paddr, size_t size) > { > - void *vaddr = phys_to_virt(paddr); > - > - THEAD_CMO_OP(inval, vaddr, size, riscv_cbom_block_size); > + THEAD_CMO_OP(inval, paddr, size, riscv_cbom_block_size); > } > > static void thead_errata_cache_wback(phys_addr_t paddr, size_t size) > { > - void *vaddr = phys_to_virt(paddr); > - > - THEAD_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); > + THEAD_CMO_OP(clean, paddr, size, riscv_cbom_block_size); > } > > static void thead_errata_cache_wback_inv(phys_addr_t paddr, size_t size) > { > - void *vaddr = phys_to_virt(paddr); > - > - THEAD_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); > + THEAD_CMO_OP(flush, paddr, size, riscv_cbom_block_size); > } > > static const struct riscv_nonstd_cache_ops thead_errata_cmo_ops = { > -- > 2.40.1 > Thx, Reviewed-by: Guo Ren <guoren@kernel.org>
diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c index 3fefeb1b456e..632557f36b19 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -58,9 +58,9 @@ static bool errata_probe_pbmt(unsigned int stage, * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | * 0000000 11001 00000 000 00000 0001011 */ -#define THEAD_inval_A0 ".long 0x0265000b" -#define THEAD_clean_A0 ".long 0x0255000b" -#define THEAD_flush_A0 ".long 0x0275000b" +#define THEAD_inval_A0 ".long 0x02a5000b" +#define THEAD_clean_A0 ".long 0x0295000b" +#define THEAD_flush_A0 ".long 0x02b5000b" #define THEAD_SYNC_S ".long 0x0190000b" #define THEAD_CMO_OP(_op, _start, _size, _cachesize) \ @@ -79,23 +79,17 @@ asm volatile("mv a0, %1\n\t" \ static void thead_errata_cache_inv(phys_addr_t paddr, size_t size) { - void *vaddr = phys_to_virt(paddr); - - THEAD_CMO_OP(inval, vaddr, size, riscv_cbom_block_size); + THEAD_CMO_OP(inval, paddr, size, riscv_cbom_block_size); } static void thead_errata_cache_wback(phys_addr_t paddr, size_t size) { - void *vaddr = phys_to_virt(paddr); - - THEAD_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); + THEAD_CMO_OP(clean, paddr, size, riscv_cbom_block_size); } static void thead_errata_cache_wback_inv(phys_addr_t paddr, size_t size) { - void *vaddr = phys_to_virt(paddr); - - THEAD_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); + THEAD_CMO_OP(flush, paddr, size, riscv_cbom_block_size); } static const struct riscv_nonstd_cache_ops thead_errata_cmo_ops = {
T-HEAD CPUs such as C906/C910/C920 support phy address based CMO, use them so that we don't need to convert to virt address. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> --- arch/riscv/errata/thead/errata.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-)