From patchwork Sun Oct 1 10:34:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13405361 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 16ED8E748E9 for ; Sun, 1 Oct 2023 10:46:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=L6vXunRpdm4ugUupIegIm5r+KSK18CTc+qibxqWABjs=; b=Tnjx0wcZB8m9mr uznpUC3JDPmuE/QPn4FNRd/NCJdnfCz6RF24Abpliue/5jOZhasuNIAb9gfJP9kzJi9G1gfNbaVrv 4cOqy2/5zjUd7EqVysnVf4aVUEfQ54a703Gohf6HGqK30TW6bUfWYbJOxnTi5eHaykQtcCSD8A1s5 UAgHNDB+ticdQU0DrpvlGDGvs98F1ySBK9LS99dJidUgtoAR+SxFA1BOIMM3ZwwW428EOS5sh4OH0 CFbxRu1VSAGQKwVBHQyyDzldxgN10QU9rcw7uEB3uc0dtpG8Sfe9T4rkcjRiwI5PydbL/TsWKSplj pRitPQP1AdVgIHqpXhsA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qmtyM-00Ay5R-0a; Sun, 01 Oct 2023 10:46:50 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qmtyJ-00Ay3M-0O for linux-riscv@lists.infradead.org; Sun, 01 Oct 2023 10:46:49 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by ams.source.kernel.org (Postfix) with ESMTP id 40DF1B808C0; Sun, 1 Oct 2023 10:46:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 87CD2C433C7; Sun, 1 Oct 2023 10:46:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1696157200; bh=qzR32gMwqLa17IpLtlTXacrXoBXks+o3rMWn8BtgPT4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oWMkJN6TASGuqSj1ckYx9rlqW8PyzufTainBHUKNuDudf/9J6MqGNc/nnhFRYY6VB sFiPvIg7hp8ixx5AsnFiX9vCoXlQwWcQjD8eegcnSBAEH7+YL1zii4F+YHCdTMQn7m Pgnrzh/SWyow94vQq6hDjKOl4whgjOBgtr8kvAVGnrEyIWHHQMNwUTbOfGPlSUMTBn OASAXWm8fjDenqygce35YaWFaQkunJ7OR7iBX0HjRwLLjC0b+CIg00cgnup9iqrgbA jeOTryhmi2osIN/R6hjNGE+wMdUQSPWzi64R5altT2reUbJCzugsy3j7fPefdQiAZK n0pYF0hK2bE+g== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Guo Ren , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/2] riscv: errata: thead: use pa based instructions for CMO Date: Sun, 1 Oct 2023 18:34:33 +0800 Message-Id: <20231001103433.3187-3-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20231001103433.3187-1-jszhang@kernel.org> References: <20231001103433.3187-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231001_034647_306246_8DC88480 X-CRM114-Status: UNSURE ( 7.77 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T-HEAD CPUs such as C906/C910/C920 support phy address based CMO, use them so that we don't need to convert to virt address. Signed-off-by: Jisheng Zhang --- arch/riscv/errata/thead/errata.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c index 3fefeb1b456e..632557f36b19 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -58,9 +58,9 @@ static bool errata_probe_pbmt(unsigned int stage, * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | * 0000000 11001 00000 000 00000 0001011 */ -#define THEAD_inval_A0 ".long 0x0265000b" -#define THEAD_clean_A0 ".long 0x0255000b" -#define THEAD_flush_A0 ".long 0x0275000b" +#define THEAD_inval_A0 ".long 0x02a5000b" +#define THEAD_clean_A0 ".long 0x0295000b" +#define THEAD_flush_A0 ".long 0x02b5000b" #define THEAD_SYNC_S ".long 0x0190000b" #define THEAD_CMO_OP(_op, _start, _size, _cachesize) \ @@ -79,23 +79,17 @@ asm volatile("mv a0, %1\n\t" \ static void thead_errata_cache_inv(phys_addr_t paddr, size_t size) { - void *vaddr = phys_to_virt(paddr); - - THEAD_CMO_OP(inval, vaddr, size, riscv_cbom_block_size); + THEAD_CMO_OP(inval, paddr, size, riscv_cbom_block_size); } static void thead_errata_cache_wback(phys_addr_t paddr, size_t size) { - void *vaddr = phys_to_virt(paddr); - - THEAD_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); + THEAD_CMO_OP(clean, paddr, size, riscv_cbom_block_size); } static void thead_errata_cache_wback_inv(phys_addr_t paddr, size_t size) { - void *vaddr = phys_to_virt(paddr); - - THEAD_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); + THEAD_CMO_OP(flush, paddr, size, riscv_cbom_block_size); } static const struct riscv_nonstd_cache_ops thead_errata_cmo_ops = {