diff mbox series

[v2,3/8] riscv: report perf event for misaligned fault

Message ID 20231004151405.521596-4-cleger@rivosinc.com (mailing list archive)
State Accepted
Commit 89c12fecdc4d46c1f08a81dab5d305304cc626eb
Headers show
Series Add support to handle misaligned accesses in S-mode | expand

Checks

Context Check Description
conchuod/vmtest-for-next-PR fail PR summary
conchuod/patch-3-test-13 success .github/scripts/patches/verify_signedoff.sh
conchuod/patch-3-test-1 success .github/scripts/patches/build_rv32_defconfig.sh
conchuod/patch-3-test-2 success .github/scripts/patches/build_rv64_clang_allmodconfig.sh
conchuod/patch-3-test-3 success .github/scripts/patches/build_rv64_gcc_allmodconfig.sh
conchuod/patch-3-test-4 success .github/scripts/patches/build_rv64_nommu_k210_defconfig.sh
conchuod/patch-3-test-5 success .github/scripts/patches/build_rv64_nommu_virt_defconfig.sh
conchuod/patch-3-test-6 success .github/scripts/patches/checkpatch.sh
conchuod/patch-3-test-7 success .github/scripts/patches/dtb_warn_rv64.sh
conchuod/patch-3-test-8 success .github/scripts/patches/header_inline.sh
conchuod/patch-3-test-9 success .github/scripts/patches/kdoc.sh
conchuod/patch-3-test-10 success .github/scripts/patches/module_param.sh
conchuod/patch-3-test-11 success .github/scripts/patches/verify_fixes.sh
conchuod/patch-3-test-12 success .github/scripts/patches/verify_signedoff.sh

Commit Message

Clément Léger Oct. 4, 2023, 3:14 p.m. UTC
Add missing calls to account for misaligned fault event using
perf_sw_event().

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 arch/riscv/kernel/traps_misaligned.c | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Björn Töpel Oct. 4, 2023, 5:02 p.m. UTC | #1
Clément Léger <cleger@rivosinc.com> writes:

> Add missing calls to account for misaligned fault event using
> perf_sw_event().
>
> Signed-off-by: Clément Léger <cleger@rivosinc.com>

Reviewed-by: Björn Töpel <bjorn@rivosinc.com>
diff mbox series

Patch

diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index 9daed7d756ae..804f6c5e0e44 100644
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -6,6 +6,7 @@ 
 #include <linux/init.h>
 #include <linux/mm.h>
 #include <linux/module.h>
+#include <linux/perf_event.h>
 #include <linux/irq.h>
 #include <linux/stringify.h>
 
@@ -294,6 +295,8 @@  int handle_misaligned_load(struct pt_regs *regs)
 	unsigned long addr = regs->badaddr;
 	int i, fp = 0, shift = 0, len = 0;
 
+	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
+
 	if (get_insn(regs, epc, &insn))
 		return -1;
 
@@ -382,6 +385,8 @@  int handle_misaligned_store(struct pt_regs *regs)
 	unsigned long addr = regs->badaddr;
 	int i, len = 0;
 
+	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
+
 	if (get_insn(regs, epc, &insn))
 		return -1;