From patchwork Mon Oct 9 09:37:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13413250 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39A1EE95A96 for ; Mon, 9 Oct 2023 09:40:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=oIHp8N2ZIahrIvRJIo1+zFzq04nXWIjenSLbU07D8mc=; b=l2HTYxO0Qu85mY GowFTu4rzhQQ77jSHrTLvAcuoehr4/Y6BHV0n/1PUkU1pRDmf+NfRgEkPUJm8GNEllJiFeGd7VYda fgY3BhtA/aCIckYiwLOdpIrOc/LI3yNLZvbEh+HJVNvp0rojsOQa8Bx5qZg/yKHXg1QSAxyPHOMXT 8ZP8ObZZGDqK5Bz3nC/7E8+2Zwyp97onaLrqk9zpUXp5qiqQPx7NZB9Vh7NuRjftNdknwu2jN1QQ9 qCX/Ks5OMw33R7+szYsoCBhVfXdKpGApsLM0FAmgVNtnDU15vUFEltff5wG5Gb/oaRguRq21pURAB tvw5OHDd01hlvQZrvrPA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qpmk1-00A75C-1a; Mon, 09 Oct 2023 09:39:57 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qpmjw-00A73p-3C for linux-riscv@lists.infradead.org; Mon, 09 Oct 2023 09:39:55 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1696844392; x=1728380392; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IFHxvV76DQ6UmIeCUgXcZ1c22Kaa/5MKcYvW0mJV6W4=; b=R0F9X0df3i8N8I0PB4NDwxa6Q3Jt6Kg4KVnZ1v5ZowvzR8Tmg7gHT1cN Q93uYfCarYhuO6kBX2421IEy5eUi3Hm53Mv8Lj56Me+S7mEcD9dJENjN5 cvBGS9Vf0zrxbYQX28K+zHQvEB1NFWFYDyWLd7FJzMWUbQsCd4sDRryWr QNHCxwl1zUmMwdrHbqZ3kRTPXGCzeFcMjuBq/r6sGSkYRhW6FoG3B/97P TnWEkpNHmKq2qMlq6vHUgIrbQZKhRDN8IuGkpL1HWLnJ1Z9YKB/dLFBfg pQ5bOJx7Vgkgm+3idqToYEkQZ3DMSXzyyuvRE28CMl9BxTwLP4B51wk14 A==; X-CSE-ConnectionGUID: ss/kXsifRKO4Oj8Q887AdA== X-CSE-MsgGUID: Npy1MPcYTa+Nx9vgamJKCQ== X-ThreatScanner-Verdict: Negative X-IronPort-AV: E=Sophos;i="6.03,210,1694761200"; d="scan'208";a="9216030" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 09 Oct 2023 02:39:48 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 9 Oct 2023 02:39:47 -0700 Received: from wendy.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 9 Oct 2023 02:39:43 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Paul Walmsley" , Palmer Dabbelt , Albert Ou , Chen-Yu Tsai , "Jernej Skrabec" , Samuel Holland , Daire McNamara , Geert Uytterhoeven , Magnus Damm , "Emil Renner Berthing" , Jisheng Zhang , Guo Ren , Fu Wei , Chen Wang , , , , Subject: [PATCH v3 1/6] riscv: dts: microchip: convert isa detection to new properties Date: Mon, 9 Oct 2023 10:37:45 +0100 Message-ID: <20231009-rockfish-wistful-3e0106be968c@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231009-approve-verbalize-ce9324858e76@wendy> References: <20231009-approve-verbalize-ce9324858e76@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2237; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=IFHxvV76DQ6UmIeCUgXcZ1c22Kaa/5MKcYvW0mJV6W4=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKnKJ1/udH4lYKXuf7K3PXt9hU+nK5Ps4f+8GzyeMSVuuFD5 ePK6jlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAExEyZaRYfZrtus/Es92XF/zJnGLa/ mU1NMNFeGn9/adOlukJx/bNJ2RYY1cNOfG6T/efnnT8dxvfnjXQmevbBnXI0mGN0yC7nt+4AAA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231009_023953_108075_FB0D0BF3 X-CRM114-Status: UNSURE ( 8.23 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Convert the PolarFire SoC devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 104504352e99..a6faf24f1dba 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -22,6 +22,9 @@ cpu0: cpu@0 { i-cache-size = <16384>; reg = <0>; riscv,isa = "rv64imac"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", + "zihpm"; clocks = <&clkcfg CLK_CPU>; status = "disabled"; @@ -48,6 +51,9 @@ cpu1: cpu@1 { mmu-type = "riscv,sv39"; reg = <1>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -76,6 +82,9 @@ cpu2: cpu@2 { mmu-type = "riscv,sv39"; reg = <2>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -104,6 +113,9 @@ cpu3: cpu@3 { mmu-type = "riscv,sv39"; reg = <3>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -132,6 +144,9 @@ cpu4: cpu@4 { mmu-type = "riscv,sv39"; reg = <4>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>;