From patchwork Mon Oct 9 09:37:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13413253 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3175AE95A96 for ; Mon, 9 Oct 2023 09:44:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=LB9Qx2gqcgI5Lgg5XOBz/Uc4NKjWkxE680G9kq3Puqo=; b=a/2qb0LedovZsl Q9kPmOMapyhiPLNt9L0ulECJ97H59vlwLyk1GFs+uo6kf03tlZr18A9Gx7dyUCjXEj04TcHostGSG NoNwbBZ+na2C5LRy7tudX4+8zdvlQxLQeWQPRwQHWn2bVanTE9C/ECLiRuLJ81c0MmuSYNhmbNlL6 wniHvl8FUmIeqBB7yYup+u3uKeAytDFW82QVkuVhWsdqBHf1rcJAoK5bHPwewI2/YV+haK7SGuMFg 7xiM3iB7roDkeUH5oqBSPxC2xrN5gK+AxQpuZXoTVcjJCb+PZjWSxZzEw9gOkEtZTwPtj/Lr0C1e2 zJYV0cQpPwGH7EIVYxNg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qpmoY-00A7oV-1y; Mon, 09 Oct 2023 09:44:38 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qpmoV-00A7nY-1Q for linux-riscv@lists.infradead.org; Mon, 09 Oct 2023 09:44:37 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1696844675; x=1728380675; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZtQo0AOZyII3HHuuFcu57y2laopGel6BHtBnxFpkQGE=; b=T4FAYotpX4TqsCmLX6gdWUNZal61iEp4RtP2YMti04F1+XdUVJGKuy/D ES1xaHT/LdoAa2HjWC2gAyIAxT2d5RWMawdX+1m5NmcOnK9/hKPsoYvq1 YPLaSmd0yEpnmSATnpFWqipksZDBbWiB/2i1IGHNU8T1IcLpS7o6BRfts ZVTBwPwr1ycOAvLOKQDlsgp031pN8Pt/dCWMH1bIOvI60Iztm/uQgGRde PsXpjK9rJQhTNZe0CL4fr58+zU/RQHPAQ+B6sAil9Zned5gKAWKCvmqTg XPVzAZknKrXZWw+XREYcs213y33bx1wkEroxiLpMIKQOB9qo1Fv7sB/V4 w==; X-CSE-ConnectionGUID: ExFLQ79KS3SJV7MWrGq2IQ== X-CSE-MsgGUID: 22lzby5eTqOrBYjjx8mW8w== X-ThreatScanner-Verdict: Negative X-IronPort-AV: E=Sophos;i="6.03,210,1694761200"; d="scan'208";a="239927134" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 09 Oct 2023 02:40:04 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 9 Oct 2023 02:39:57 -0700 Received: from wendy.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 9 Oct 2023 02:39:52 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Paul Walmsley" , Palmer Dabbelt , Albert Ou , Chen-Yu Tsai , "Jernej Skrabec" , Samuel Holland , Daire McNamara , Geert Uytterhoeven , Magnus Damm , "Emil Renner Berthing" , Jisheng Zhang , Guo Ren , Fu Wei , Chen Wang , , , , Subject: [PATCH v3 3/6] riscv: dts: starfive: convert isa detection to new properties Date: Mon, 9 Oct 2023 10:37:47 +0100 Message-ID: <20231009-unloader-april-e613cf388354@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231009-approve-verbalize-ce9324858e76@wendy> References: <20231009-approve-verbalize-ce9324858e76@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3464; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=ZtQo0AOZyII3HHuuFcu57y2laopGel6BHtBnxFpkQGE=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKnKJ19Gmmcu9DRV5c/f9mdBn9mzNwKr+AXltulnM124mtn5 WC28o5SFQYyDQVZMkSXxdl+L1Po/Ljuce97CzGFlAhnCwMUpABMJaWVk2NKv/eHelw8y/q+8WD2qct fai2+YtGP1h/m6XSE2UfIaTxgZvouU8wXJz9q1PcLy9mKdv9nv1p3sPf+i9Yl1qGNH2/kMFgA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231009_024435_489474_671AFBDE X-CRM114-Status: UNSURE ( 7.87 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Convert the jh7100 and jh7110 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 6 ++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 15 +++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 35ab54fb235f..e68cafe7545f 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -33,6 +33,9 @@ U74_0: cpu@0 { i-tlb-size = <32>; mmu-type = "riscv,sv39"; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; cpu0_intc: interrupt-controller { @@ -58,6 +61,9 @@ U74_1: cpu@1 { i-tlb-size = <32>; mmu-type = "riscv,sv39"; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; cpu1_intc: interrupt-controller { diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 9f31dec57c0d..45213cdf50dc 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -28,6 +28,9 @@ S7_0: cpu@0 { i-cache-size = <16384>; next-level-cache = <&ccache>; riscv,isa = "rv64imac_zba_zbb"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr", + "zifencei", "zihpm"; status = "disabled"; cpu0_intc: interrupt-controller { @@ -54,6 +57,9 @@ U74_1: cpu@1 { mmu-type = "riscv,sv39"; next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; @@ -84,6 +90,9 @@ U74_2: cpu@2 { mmu-type = "riscv,sv39"; next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; @@ -114,6 +123,9 @@ U74_3: cpu@3 { mmu-type = "riscv,sv39"; next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; @@ -144,6 +156,9 @@ U74_4: cpu@4 { mmu-type = "riscv,sv39"; next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;