diff mbox series

[v1,11/13] riscv: add ISA extension probing for Zvfh[min]

Message ID 20231011111438.909552-12-cleger@rivosinc.com (mailing list archive)
State Superseded
Headers show
Series riscv: report more ISA extensions through hwprobe | expand

Checks

Context Check Description
conchuod/vmtest-fixes-PR fail merge-conflict
conchuod/vmtest-for-next-PR fail PR summary
conchuod/patch-11-test-1 success .github/scripts/patches/build_rv32_defconfig.sh
conchuod/patch-11-test-2 success .github/scripts/patches/build_rv64_clang_allmodconfig.sh
conchuod/patch-11-test-3 success .github/scripts/patches/build_rv64_gcc_allmodconfig.sh
conchuod/patch-11-test-4 success .github/scripts/patches/build_rv64_nommu_k210_defconfig.sh
conchuod/patch-11-test-5 success .github/scripts/patches/build_rv64_nommu_virt_defconfig.sh
conchuod/patch-11-test-6 warning .github/scripts/patches/checkpatch.sh
conchuod/patch-11-test-7 success .github/scripts/patches/dtb_warn_rv64.sh
conchuod/patch-11-test-8 success .github/scripts/patches/header_inline.sh
conchuod/patch-11-test-9 success .github/scripts/patches/kdoc.sh
conchuod/patch-11-test-10 success .github/scripts/patches/module_param.sh
conchuod/patch-11-test-11 success .github/scripts/patches/verify_fixes.sh
conchuod/patch-11-test-12 success .github/scripts/patches/verify_signedoff.sh

Commit Message

Clément Léger Oct. 11, 2023, 11:14 a.m. UTC
Add probing for Zvfh[min] ISA extension[1] which were ratified in
june 2023 around commit e2ccd0548d6c ("Remove draft warnings from
Zvfh[min]") in riscv-v-spec[2].

[1] https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/view
[2] https://github.com/riscv/riscv-v-spec/commits/e2ccd0548d6c

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 arch/riscv/include/asm/hwcap.h | 2 ++
 arch/riscv/kernel/cpufeature.c | 2 ++
 2 files changed, 4 insertions(+)
diff mbox series

Patch

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 1f09b8b3da2a..ea141cfb8f9c 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -77,6 +77,8 @@ 
 #define RISCV_ISA_EXT_ZFH		59
 #define RISCV_ISA_EXT_ZFHMIN		60
 #define RISCV_ISA_EXT_ZIHINTNTL		61
+#define RISCV_ISA_EXT_ZVFH		62
+#define RISCV_ISA_EXT_ZVFHMIN		63
 
 #define RISCV_ISA_EXT_MAX		64
 
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 136e90263ba2..f17b9aca5fba 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -179,6 +179,8 @@  const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
 	__RISCV_ISA_EXT_DATA(zvbb, RISCV_ISA_EXT_ZVBB),
 	__RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
+	__RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
+	__RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
 	__RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
 	__RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG),
 	__RISCV_ISA_EXT_DATA(zvkn, RISCV_ISA_EXT_ZVKN),