@@ -77,6 +77,8 @@
#define RISCV_ISA_EXT_ZFH 59
#define RISCV_ISA_EXT_ZFHMIN 60
#define RISCV_ISA_EXT_ZIHINTNTL 61
+#define RISCV_ISA_EXT_ZVFH 62
+#define RISCV_ISA_EXT_ZVFHMIN 63
#define RISCV_ISA_EXT_MAX 64
@@ -179,6 +179,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
__RISCV_ISA_EXT_DATA(zvbb, RISCV_ISA_EXT_ZVBB),
__RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
+ __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
+ __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
__RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
__RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG),
__RISCV_ISA_EXT_DATA(zvkn, RISCV_ISA_EXT_ZVKN),
Add probing for Zvfh[min] ISA extension[1] which were ratified in june 2023 around commit e2ccd0548d6c ("Remove draft warnings from Zvfh[min]") in riscv-v-spec[2]. [1] https://drive.google.com/file/d/1_Yt60HGAf1r1hx7JnsIptw0sqkBd9BQ8/view [2] https://github.com/riscv/riscv-v-spec/commits/e2ccd0548d6c Signed-off-by: Clément Léger <cleger@rivosinc.com> --- arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpufeature.c | 2 ++ 2 files changed, 4 insertions(+)