diff mbox series

[v1,05/13] riscv: add ISA extension probing for Zfh/Zfhmin

Message ID 20231011111438.909552-6-cleger@rivosinc.com (mailing list archive)
State Superseded
Headers show
Series riscv: report more ISA extensions through hwprobe | expand

Checks

Context Check Description
conchuod/patch-5-test-13 success .github/scripts/patches/verify_signedoff.sh
conchuod/vmtest-for-next-PR fail PR summary
conchuod/patch-5-test-1 success .github/scripts/patches/build_rv32_defconfig.sh
conchuod/patch-5-test-2 fail .github/scripts/patches/build_rv64_clang_allmodconfig.sh
conchuod/patch-5-test-3 success .github/scripts/patches/build_rv64_gcc_allmodconfig.sh
conchuod/patch-5-test-4 success .github/scripts/patches/build_rv64_nommu_k210_defconfig.sh
conchuod/patch-5-test-5 success .github/scripts/patches/build_rv64_nommu_virt_defconfig.sh
conchuod/patch-5-test-6 success .github/scripts/patches/checkpatch.sh
conchuod/patch-5-test-7 success .github/scripts/patches/dtb_warn_rv64.sh
conchuod/patch-5-test-8 success .github/scripts/patches/header_inline.sh
conchuod/patch-5-test-9 success .github/scripts/patches/kdoc.sh
conchuod/patch-5-test-10 success .github/scripts/patches/module_param.sh
conchuod/patch-5-test-11 success .github/scripts/patches/verify_fixes.sh
conchuod/patch-5-test-12 success .github/scripts/patches/verify_signedoff.sh

Commit Message

Clément Léger Oct. 11, 2023, 11:14 a.m. UTC
Add probing for Zvfh/Zfhmin ISA extensions[1].

[1] https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/view

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 arch/riscv/include/asm/hwcap.h | 2 ++
 arch/riscv/kernel/cpufeature.c | 2 ++
 2 files changed, 4 insertions(+)
diff mbox series

Patch

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 4e46981ac6c8..35f00401afc8 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -74,6 +74,8 @@ 
 #define RISCV_ISA_EXT_ZVKSH		56
 #define RISCV_ISA_EXT_ZVKSG		57
 #define RISCV_ISA_EXT_ZVKT		58
+#define RISCV_ISA_EXT_ZFH		59
+#define RISCV_ISA_EXT_ZFHMIN		60
 
 #define RISCV_ISA_EXT_MAX		64
 
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 859d647f3ced..9ee7814641a4 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -171,6 +171,8 @@  const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI),
 	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
 	__RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
+	__RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
+	__RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
 	__RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
 	__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
 	__RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),