[v2,08/19] riscv: add ISA extension parsing for Zfh/Zfhmin

Commit Message

Clément Léger Oct. 17, 2023, 1:14 p.m. UTC

Add parsing for Zvfh/Zfhmin ISA extensions[1].

Link: https://drive.google.com/file/d/1z3tQQLm5ALsAD77PM0l0CHnapxWCeVzP/view [1]
Signed-off-by: Clément Léger <[e-mail]>
---
 arch/riscv/include/asm/hwcap.h | 4 +++-
 arch/riscv/kernel/cpufeature.c | 2 ++
 2 files changed, 5 insertions(+), 1 deletion(-)

Comments

Evan Green Oct. 18, 2023, 5:28 p.m. UTC | #1

On Tue, Oct 17, 2023 at 6:15 AM Clément Léger <[e-mail]> wrote:
>
> Add parsing for Zvfh/Zfhmin ISA extensions[1].

Typo: s/Zvfh/Zfh/. Other than that:

Reviewed-by: Evan Green <[e-mail]>

Patch

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index a2fac23b0cc0..bead05cb0df2 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -79,8 +79,10 @@ 
 #define RISCV_ISA_EXT_ZVKSED		61
 #define RISCV_ISA_EXT_ZVKSH		62
 #define RISCV_ISA_EXT_ZVKT		63
+#define RISCV_ISA_EXT_ZFH		64
+#define RISCV_ISA_EXT_ZFHMIN		65
 
-#define RISCV_ISA_EXT_MAX		64
+#define RISCV_ISA_EXT_MAX		128
 
 #ifdef CONFIG_RISCV_M_MODE
 #define RISCV_ISA_EXT_SxAIA		RISCV_ISA_EXT_SMAIA
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 8cf0b8b442ae..68914b5e2df9 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -244,6 +244,8 @@  const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI),
 	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
 	__RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
+	__RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),
+	__RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN),
 	__RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
 	__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
 	__RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),