From patchwork Sun Oct 22 15:18:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 13431870 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 347F7C001DF for ; Sun, 22 Oct 2023 15:23:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Cc:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=bVgmdsgpLsefk0eZj+YSrf7Oom7idkawTx5R+YFFjEo=; b=pHAZJaKxIzNNrW Pok0r7StvQua7dy6g71iBYF1LaVALHOIwXNOvSwlFB1Ye/b0jDYBQHzNIwFTI3dRs9LiFL9SAm6RS EgEnbEdw0igYdj4yosI3BvIjuqkCOe3lu9Gyis6EEIPkvCvGcxOJqFhxH6iTOdiHaxtVXyF07/HHE NCZLPC/cau1UqKiQCjn0eYa7WUDtWdB4F8bEYpID7emi1I6VjZGEZd4QahrHPjYSqN0r39IBKHHZI f61T7oa1gxaWqCn+nH9H2+nD2jF1GVI5XsHscEyU0W637Uyc51Ikg9foyaQRRyij5AqCs3LIx03nQ jPG5Exu3quBajSuFxqtw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1quaIu-005bXS-1G; Sun, 22 Oct 2023 15:23:48 +0000 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1quaIk-005bUo-1B; Sun, 22 Oct 2023 15:23:39 +0000 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 39MFMYWu032724; Sun, 22 Oct 2023 23:22:34 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Sun, 22 Oct 2023 23:22:30 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 04/13] dt-bindings: riscv: Add Andes interrupt controller compatible string Date: Sun, 22 Oct 2023 23:18:49 +0800 Message-ID: <20231022151858.2479969-5-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231022151858.2479969-1-peterlin@andestech.com> References: <20231022151858.2479969-1-peterlin@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 39MFMYWu032724 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231022_082338_858299_4A6539A8 X-CRM114-Status: UNSURE ( 7.71 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add "andestech,cpu-intc" compatible string which indicates that Andes specific local interrupt is supported on the core, e.g. AX45MP cores have 3 types of non-standard local interrupt can be handled in supervisor mode: - Slave port ECC error interrupt - Bus write transaction error interrupt - Performance monitor overflow interrupt These interrupts are enabled/disabled via a custom register SLIE instead of the standard interrupt enable register SIE. Signed-off-by: Yu Chien Peter Lin --- Changes v1 -> v2: - New patch Changes v2 -> v3: - Updated commit message - Fixed possible compatibles for Andes INTC --- Documentation/devicetree/bindings/riscv/cpus.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 97e8441eda1c..4c1bbcf07406 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -99,7 +99,12 @@ properties: const: 1 compatible: - const: riscv,cpu-intc + oneOf: + - items: + - enum: + - andestech,cpu-intc + - const: riscv,cpu-intc + - const: riscv,cpu-intc interrupt-controller: true