| Message ID | 20231022154135.3746-1-jszhang@kernel.org (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | riscv: dts: thead: convert isa detection to new properties | expand |
On Sun, Oct 22, 2023 at 11:41:35PM +0800, Jisheng Zhang wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > Convert the th1520 devicetrees to use the new properties > "riscv,isa-base" & "riscv,isa-extensions". > For compatibility with other projects, "riscv,isa" remains. > > Reviewed-by: Jisheng Zhang <jszhang@kernel.org> > Acked-by: Guo Ren <guoren@kernel.org> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > > Hi Arnd, > > This is the only one thead patch for v6.7, could you please apply it > directly? FYI, this is missing your signoff, since you are resending my patch. Cheers, Conor.
On Mon, Oct 23, 2023 at 09:27:07AM +0100, Conor Dooley wrote: > On Sun, Oct 22, 2023 at 11:41:35PM +0800, Jisheng Zhang wrote: > > From: Conor Dooley <conor.dooley@microchip.com> > > > > Convert the th1520 devicetrees to use the new properties > > "riscv,isa-base" & "riscv,isa-extensions". > > For compatibility with other projects, "riscv,isa" remains. > > > > Reviewed-by: Jisheng Zhang <jszhang@kernel.org> > > Acked-by: Guo Ren <guoren@kernel.org> > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > > --- > > > > Hi Arnd, > > > > This is the only one thead patch for v6.7, could you please apply it > > directly? > > FYI, this is missing your signoff, since you are resending my patch. > Hi Conor, Today I noticed that Arnd has tagged for-next for 6.7, so I guess I missed the 6.7 PR, sorry. And I also noticed that Arnd has queued the thead dma-noncoherent patch for 6.7(which is expected in rc7 :) because I didn't explictly mark the target. I will take care this kind of PR/directly_merge target in future. I expected a large dt and driver changes in the comming development window, for example, usb/eth/emmc and so on, so I'll queue your patch into my for-next tree once linux6.7-rc1 is released. Thanks
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index ce708183b6f6..723f65487246 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -20,6 +20,9 @@ c910_0: cpu@0 { compatible = "thead,c910", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <0>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -41,6 +44,9 @@ c910_1: cpu@1 { compatible = "thead,c910", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <1>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -62,6 +68,9 @@ c910_2: cpu@2 { compatible = "thead,c910", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <2>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -83,6 +92,9 @@ c910_3: cpu@3 { compatible = "thead,c910", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <3>; i-cache-block-size = <64>; i-cache-size = <65536>;