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([2a01:e0a:999:a3a0:b380:32be:257:5381]) by smtp.gmail.com with ESMTPSA id r9-20020a056000014900b003232f167df5sm14316589wrx.108.2023.10.26.07.31.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Oct 2023 07:31:27 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Himanshu Chauhan , Xu Lu Subject: [RFC PATCH 1/3] riscv: add SBI SSE extension definitions Date: Thu, 26 Oct 2023 16:31:20 +0200 Message-ID: <20231026143122.279437-2-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231026143122.279437-1-cleger@rivosinc.com> References: <20231026143122.279437-1-cleger@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231026_073129_571387_F01E627D X-CRM114-Status: GOOD ( 10.55 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add needed definitions for SBI Supervisor Software Events extension [1]. This extension enables the SBI to inject events into supervisor software much like ARM SDEI. [1] https://lists.riscv.org/g/tech-prs/message/515 Signed-off-by: Clément Léger --- arch/riscv/include/asm/sbi.h | 38 ++++++++++++++++++++++++++++++++++++ arch/riscv/kernel/sbi.c | 4 ++++ 2 files changed, 42 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 5b4a1bf5f439..2e99cafe7fed 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -30,6 +30,7 @@ enum sbi_ext_id { SBI_EXT_HSM = 0x48534D, SBI_EXT_SRST = 0x53525354, SBI_EXT_PMU = 0x504D55, + SBI_EXT_SSE = 0x535345, /* Experimentals extensions must lie within this range */ SBI_EXT_EXPERIMENTAL_START = 0x08000000, @@ -236,6 +237,40 @@ enum sbi_pmu_ctr_type { /* Flags defined for counter stop function */ #define SBI_PMU_STOP_FLAG_RESET (1 << 0) +enum sbi_ext_sse_fid { + SBI_SSE_EVENT_ATTR_GET = 0, + SBI_SSE_EVENT_ATTR_SET, + SBI_SSE_EVENT_REGISTER, + SBI_SSE_EVENT_UNREGISTER, + SBI_SSE_EVENT_ENABLE, + SBI_SSE_EVENT_DISABLE, + SBI_SSE_EVENT_COMPLETE, + SBI_SSE_EVENT_SIGNAL, +}; + +#define SBI_SSE_EVENT_LOCAL_RAS 0x00000000 +#define SBI_SSE_EVENT_GLOBAL_RAS 0x00008000 +#define SBI_SSE_EVENT_LOCAL_ASYNC_PF 0x00010000 +#define SBI_SSE_EVENT_LOCAL_PMU 0x00010001 +#define SBI_SSE_EVENT_LOCAL_DEBUG 0xffff3fff +#define SBI_SSE_EVENT_GLOBAL_DEBUG 0xffffbfff + +#define SBI_SSE_EVENT_GLOBAL (1 << 15) +#define SBI_SSE_EVENT_PLATFORM (1 << 14) + +enum sbi_sse_event_attr { + SBI_SSE_EVENT_ATTR_STATE = 0, + SBI_SSE_EVENT_ATTR_PRIORITY, + SBI_SSE_EVENT_ATTR_INJECTION, + SBI_SSE_EVENT_ATTR_HART_ID, + SBI_SSE_EVENT_ATTR_RAW_PENDING_STATUS, +}; + +enum sbi_sse_event_handler_sts { + SBI_SSE_HANDLER_SUCCESS = 0, + SBI_SSE_HANDLER_FAILED, +}; + #define SBI_SPEC_VERSION_DEFAULT 0x1 #define SBI_SPEC_VERSION_MAJOR_SHIFT 24 #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f @@ -251,6 +286,9 @@ enum sbi_pmu_ctr_type { #define SBI_ERR_ALREADY_AVAILABLE -6 #define SBI_ERR_ALREADY_STARTED -7 #define SBI_ERR_ALREADY_STOPPED -8 +#define SBI_ERR_INVALID_STATE -10 +#define SBI_ERR_BAD_RANGE -11 +#define SBI_ERR_BUSY -12 extern unsigned long sbi_spec_version; struct sbiret { diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index c672c8ba9a2a..13b63b383d4e 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -56,9 +56,13 @@ int sbi_err_map_linux_errno(int err) case SBI_ERR_DENIED: return -EPERM; case SBI_ERR_INVALID_PARAM: + case SBI_ERR_BAD_RANGE: + case SBI_ERR_INVALID_STATE: return -EINVAL; case SBI_ERR_INVALID_ADDRESS: return -EFAULT; + case SBI_ERR_BUSY: + return -EBUSY; case SBI_ERR_NOT_SUPPORTED: case SBI_ERR_FAILURE: default: