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Wed, 01 Nov 2023 19:49:26 -0700 (PDT) Received: from [127.0.1.1] ([2601:1c2:1800:f680:7e4c:4d4e:6943:bc0f]) by smtp.gmail.com with ESMTPSA id n4-20020a170902e54400b001b850c9d7b3sm1925787plf.249.2023.11.01.19.49.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 19:49:25 -0700 (PDT) From: Drew Fustini Date: Wed, 01 Nov 2023 19:48:58 -0700 Subject: [PATCH v4 7/7] riscv: dts: thead: Enable LicheePi 4A eMMC and microSD MIME-Version: 1.0 Message-Id: <20231101-th1520-mmc-v4-7-86e0216b5994@baylibre.com> References: <20231101-th1520-mmc-v4-0-86e0216b5994@baylibre.com> In-Reply-To: <20231101-th1520-mmc-v4-0-86e0216b5994@baylibre.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Adrian Hunter , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1698893345; l=1102; i=dfustini@baylibre.com; s=20230430; h=from:subject:message-id; bh=vZkA/Rp2zWEJvsAGA/badfpHmHgx6/3DqqLzYe2IxQc=; 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Set the frequency for the sdhci clock. Signed-off-by: Drew Fustini --- .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index a802ab110429..94f1741435a5 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -29,6 +29,10 @@ &apb_clk { clock-frequency = <62500000>; }; +&sdhci_clk { + clock-frequency = <198000000>; +}; + &uart_sclk { clock-frequency = <100000000>; }; @@ -36,3 +40,19 @@ &uart_sclk { &dmac0 { status = "okay"; }; + +&mmc0 { + bus-width = <8>; + max-frequency = <198000000>; + mmc-hs400-1_8v; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&mmc1 { + max-frequency = <198000000>; + bus-width = <4>; + status = "okay"; +};