From patchwork Wed Nov 22 09:42:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13464476 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2C8F2C61D9B for ; Wed, 22 Nov 2023 09:44:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+RUfRZJJWaC37LSXoVRaKuOXGkmr9jS6KugCzn5ocEQ=; b=4BfULNxpflbfA/ WcJGcFoIgOONakcF+/CaJ6ypqDksYlTm3Kn0ai4H27xJMDqgS04wkIzKGf18P2mTor6Mc9A/hro3A zwkFowG9D7qultsIqf08sBzD6r7XAj0Us7GzCcAPe4gRTjfoSheFEElvn4NSEa10iyVKrwBpWgKF5 YnJqqMiSys2fDK3iyuOHcpsx3dX9mJHX0rd9/Ktzh1vWwcGJIfsa7DRoMG437p9RLbPLZkbaT6u1Y fSp/7wf3RxDbbbZZigxEB7aj8DaCIuvPWhva6fjQ2G4hShTT0ljreDHvyGHZijJS5WqHDf2PvEP/E OYBKBhyZz7WmYiGQG2Xg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r5jm5-001Fwu-1b; Wed, 22 Nov 2023 09:44:01 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1r5jlz-001FoV-2M; Wed, 22 Nov 2023 09:43:57 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by ams.source.kernel.org (Postfix) with ESMTP id 67E5DB81190; Wed, 22 Nov 2023 09:43:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1CF86C433CC; Wed, 22 Nov 2023 09:43:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1700646233; bh=Kj5ys8EZzcB9lauTa/2n/TuM+KU70CYN6cCdyA5umEU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Jo0eqnhFka9a7dffiKyy/h01WlRwGEogNuM4GOLoxUdOw9GTlY8Y8IsRwkGQAzVps ZejwMBmDzIrkQh7K7q2pQDPrZXsbBtCixxWp/qAS7BsVPKK22IOAiUXVCd05mRyTBF 4sHtlCXV5S5ajmQ08Ha0/qmbnTXoNEuvYf8Rpl3kx5lqfIJwozNKfyvlN0ixlabSCs z0tRYzkYowakVqbhA+GWa06AGpTmKfBv+oJbb2Y21eWQZergE/uRiRxQ0pVmATJcWM 102wKL6RaMwQ1C6yALuvXYKN5CI7cvjxWoE2cPJirA2ZviLOEi3nlbI0j8VIjMydt6 JEaT3JTOFHOeg== From: Mark Brown Date: Wed, 22 Nov 2023 09:42:18 +0000 Subject: [PATCH v7 08/39] arm64/gcs: Add manual encodings of GCS instructions MIME-Version: 1.0 Message-Id: <20231122-arm64-gcs-v7-8-201c483bd775@kernel.org> References: <20231122-arm64-gcs-v7-0-201c483bd775@kernel.org> In-Reply-To: <20231122-arm64-gcs-v7-0-201c483bd775@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Andrew Morton , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Arnd Bergmann , Oleg Nesterov , Eric Biederman , Kees Cook , Shuah Khan , "Rick P. Edgecombe" , Deepak Gupta , Ard Biesheuvel , Szabolcs Nagy Cc: "H.J. Lu" , Paul Walmsley , Palmer Dabbelt , Albert Ou , Florian Weimer , Christian Brauner , Thiago Jung Bauermann , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=2577; i=broonie@kernel.org; h=from:subject:message-id; bh=Kj5ys8EZzcB9lauTa/2n/TuM+KU70CYN6cCdyA5umEU=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlXcz8bXL6mSlClcxo2LLkqYujwDOa49MNEAxac 4wcHFzLkiKJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZV3M/AAKCRAk1otyXVSH 0GQIB/9o9cqptsu1ZwBDibIQWSTMXx2jyDsfuRCayo0AmyyLwhAIo2lXL771m3LtQpEJubjNSO3 PVjPlRoT2ipPWpt735Fg5NkUgjzEcT6xeT/oG5/YpHULuKMwSq9zvHV+woRV+lYiOZItIrNcgu+ GvMa1MuPADfJzXfw7QgtoClkc+6OfPC5vTsygXo0CEhRXV9O2659pBW0fQZPRmIa42fXbtTlpNK j3l29HNk16rpf+JFot2wdynC8PLWnTH38WB0LF2d+f+czqx+mOQs2STMWDPRpTF43MOm3QEIIJi SJNNHgxgi99OxRRLxuunS9Cf4qkX9bBRfInK56jnN8VLQHMW X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231122_014356_077980_6A2B4185 X-CRM114-Status: GOOD ( 15.76 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Define C callable functions for GCS instructions used by the kernel. In order to avoid ambitious toolchain requirements for GCS support these are manually encoded, this means we have fixed register numbers which will be a bit limiting for the compiler but none of these should be used in sufficiently fast paths for this to be a problem. Note that GCSSTTR is used to store to EL0. Signed-off-by: Mark Brown --- arch/arm64/include/asm/gcs.h | 51 ++++++++++++++++++++++++++++++++++++++++ arch/arm64/include/asm/uaccess.h | 22 +++++++++++++++++ 2 files changed, 73 insertions(+) diff --git a/arch/arm64/include/asm/gcs.h b/arch/arm64/include/asm/gcs.h new file mode 100644 index 000000000000..7c5e95218db6 --- /dev/null +++ b/arch/arm64/include/asm/gcs.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 ARM Ltd. + */ +#ifndef __ASM_GCS_H +#define __ASM_GCS_H + +#include +#include + +static inline void gcsb_dsync(void) +{ + asm volatile(".inst 0xd503227f" : : : "memory"); +} + +static inline void gcsstr(u64 *addr, u64 val) +{ + register u64 *_addr __asm__ ("x0") = addr; + register long _val __asm__ ("x1") = val; + + /* GCSSTTR x1, x0 */ + asm volatile( + ".inst 0xd91f1c01\n" + : + : "rZ" (_val), "r" (_addr) + : "memory"); +} + +static inline void gcsss1(u64 Xt) +{ + asm volatile ( + "sys #3, C7, C7, #2, %0\n" + : + : "rZ" (Xt) + : "memory"); +} + +static inline u64 gcsss2(void) +{ + u64 Xt; + + asm volatile( + "SYSL %0, #3, C7, C7, #3\n" + : "=r" (Xt) + : + : "memory"); + + return Xt; +} + +#endif diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index 14be5000c5a0..22e10e79f56a 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -425,4 +425,26 @@ static inline size_t probe_subpage_writeable(const char __user *uaddr, #endif /* CONFIG_ARCH_HAS_SUBPAGE_FAULTS */ +#ifdef CONFIG_ARM64_GCS + +static inline int gcssttr(unsigned long __user *addr, unsigned long val) +{ + register unsigned long __user *_addr __asm__ ("x0") = addr; + register unsigned long _val __asm__ ("x1") = val; + int err = 0; + + /* GCSSTTR x1, x0 */ + asm volatile( + "1: .inst 0xd91f1c01\n" + "2: \n" + _ASM_EXTABLE_UACCESS_ERR(1b, 2b, %w0) + : "+r" (err) + : "rZ" (_val), "r" (_addr) + : "memory"); + + return err; +} + +#endif /* CONFIG_ARM64_GCS */ + #endif /* __ASM_UACCESS_H */