Message ID | 20231122121235.827122-3-peterlin@andestech.com (mailing list archive) |
---|---|
State | Superseded |
Headers | show |
Series | Support Andes PMU extension | expand |
Context | Check | Description |
---|---|---|
conchuod/vmtest-fixes-PR | fail | merge-conflict |
On Wed, Nov 22 2023 at 20:12, Yu Chien Peter Lin wrote: > Currently, the implementation of the RISC-V INTC driver uses the > interrupt cause as hwirq and has a limitation of supporting a s/hwirq/hardware interrupt/ Please spell things out. We are not on Xitter here. > maximum of 64 hwirqs. However, according to the privileged spec, > interrupt causes >= 16 are defined for platform use. > > This limitation prevents us from fully utilizing the available This limitation prevents to fully utilize the ... > local interrupt sources. Additionally, the hwirqs used on RISC-V > are sparse, with only interrupt numbers 1, 5 and 9 (plus Sscofpmf > or T-Head's PMU irq) being currently used for supervisor mode. > > Switch to using irq_domain_create_tree() to create the radix tree > map, so a larger number of hardware interrupts can be handled.
Hi Thomas, On Fri, Dec 08, 2023 at 04:54:34PM +0100, Thomas Gleixner wrote: > On Wed, Nov 22 2023 at 20:12, Yu Chien Peter Lin wrote: > > Currently, the implementation of the RISC-V INTC driver uses the > > interrupt cause as hwirq and has a limitation of supporting a > > s/hwirq/hardware interrupt/ > > Please spell things out. We are not on Xitter here. > > > maximum of 64 hwirqs. However, according to the privileged spec, > > interrupt causes >= 16 are defined for platform use. > > > > This limitation prevents us from fully utilizing the available > > This limitation prevents to fully utilize the ... Okay, will fix. Thanks, Peter Lin
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index e8d01b14ccdd..2fdd40f2a791 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -24,10 +24,9 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs) { unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; - if (unlikely(cause >= BITS_PER_LONG)) - panic("unexpected interrupt cause"); - - generic_handle_domain_irq(intc_domain, cause); + if (generic_handle_domain_irq(intc_domain, cause)) + pr_warn_ratelimited("Failed to handle interrupt (cause: %ld)\n", + cause); } /* @@ -117,8 +116,7 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn) { int rc; - intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG, - &riscv_intc_domain_ops, NULL); + intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL); if (!intc_domain) { pr_err("unable to add IRQ domain\n"); return -ENXIO; @@ -132,8 +130,6 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn) riscv_set_intc_hwnode_fn(riscv_intc_hwnode); - pr_info("%d local interrupts mapped\n", BITS_PER_LONG); - return 0; }