diff mbox series

[RFC,4/5] RISC-V: Implement prctl call to set/get the memory consistency model

Message ID 20231124072142.2786653-5-christoph.muellner@vrull.eu (mailing list archive)
State Changes Requested
Headers show
Series RISC-V: Add dynamic TSO support | expand

Checks

Context Check Description
conchuod/vmtest-for-next-PR fail PR summary
conchuod/patch-4-test-1 fail .github/scripts/patches/build_rv32_defconfig.sh
conchuod/patch-4-test-2 fail .github/scripts/patches/build_rv64_clang_allmodconfig.sh
conchuod/patch-4-test-3 fail .github/scripts/patches/build_rv64_gcc_allmodconfig.sh
conchuod/patch-4-test-4 fail .github/scripts/patches/build_rv64_nommu_k210_defconfig.sh
conchuod/patch-4-test-5 fail .github/scripts/patches/build_rv64_nommu_virt_defconfig.sh
conchuod/patch-4-test-6 warning .github/scripts/patches/checkpatch.sh
conchuod/patch-4-test-7 success .github/scripts/patches/dtb_warn_rv64.sh
conchuod/patch-4-test-8 success .github/scripts/patches/header_inline.sh
conchuod/patch-4-test-9 success .github/scripts/patches/kdoc.sh
conchuod/patch-4-test-10 success .github/scripts/patches/module_param.sh
conchuod/patch-4-test-11 success .github/scripts/patches/verify_fixes.sh
conchuod/patch-4-test-12 success .github/scripts/patches/verify_signedoff.sh

Commit Message

Christoph Müllner Nov. 24, 2023, 7:21 a.m. UTC
From: Christoph Müllner <christoph.muellner@vrull.eu>

We can use the PR_{S,G}ET_MEMORY_CONSISTENCY_MODEL prctl calls to change
the memory consistency model at run-time if we have Ssdtso.
This patch registers RISCV_WMO and RISCV_TSO as valid arguments
for these prctl calls and implements the glue code to switch
between these.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 .../mm/dynamic-memory-consistency-model.rst   | 18 ++++++++++
 arch/riscv/include/asm/processor.h            |  7 ++++
 arch/riscv/kernel/Makefile                    |  1 +
 arch/riscv/kernel/dtso.c                      | 33 +++++++++++++++++++
 include/uapi/linux/prctl.h                    |  2 ++
 5 files changed, 61 insertions(+)
 create mode 100644 arch/riscv/kernel/dtso.c
diff mbox series

Patch

diff --git a/Documentation/mm/dynamic-memory-consistency-model.rst b/Documentation/mm/dynamic-memory-consistency-model.rst
index 21675b41ec84..4a6107a4b71f 100644
--- a/Documentation/mm/dynamic-memory-consistency-model.rst
+++ b/Documentation/mm/dynamic-memory-consistency-model.rst
@@ -56,3 +56,21 @@  Two prctl calls are defined to get/set the active memory consistency model:
     to the given model. If the architecture does not support dynamic
     memory consistency models or does not support the provided model, then
     -1 is returned, and errno is set to EINVAL.
+
+Supported memory consistency models
+===================================
+
+This section defines the memory consistency models which are supported
+by the prctl interface.
+
+RISC-V
+------
+
+RISC-V uses RVWMO (RISC-V weak memory ordering) as default memory consistency
+model. TSO (total store ordering) is another specified model and provides
+additional ordering guarantees. Switching from RVWMO to TSO (and back) is
+possible when the Ssdtso extension is available.
+
+* :c:macro:`PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO`: RISC-V weak memory ordering (default).
+
+* :c:macro:`PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO`: RISC-V total store ordering.
diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
index 79cc5e6377b8..b0c19ddb2cfb 100644
--- a/arch/riscv/include/asm/processor.h
+++ b/arch/riscv/include/asm/processor.h
@@ -146,6 +146,13 @@  extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
 #define GET_UNALIGN_CTL(tsk, addr)	get_unalign_ctl((tsk), (addr))
 #define SET_UNALIGN_CTL(tsk, val)	set_unalign_ctl((tsk), (val))
 
+#ifdef CONFIG_RISCV_ISA_SSDTSO
+#define SET_MEMORY_CONSISTENCY_MODEL(arg)	dtso_set_memory_ordering(arg)
+#define GET_MEMORY_CONSISTENCY_MODEL()		dtso_get_memory_ordering()
+extern int dtso_set_memory_consistency_model(unsigned long arg);
+extern int dtso_get_memory_consistency_model(void);
+#endif /* CONIG_RISCV_ISA_SSDTSO */
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_RISCV_PROCESSOR_H */
diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index fee22a3d1b53..17cf74ac8e21 100644
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -63,6 +63,7 @@  obj-$(CONFIG_MMU) += vdso.o vdso/
 obj-$(CONFIG_RISCV_MISALIGNED)	+= traps_misaligned.o
 obj-$(CONFIG_FPU)		+= fpu.o
 obj-$(CONFIG_RISCV_ISA_V)	+= vector.o
+obj-$(CONFIG_RISCV_ISA_SSDTSO)	+= dtso.o
 obj-$(CONFIG_SMP)		+= smpboot.o
 obj-$(CONFIG_SMP)		+= smp.o
 obj-$(CONFIG_SMP)		+= cpu_ops.o
diff --git a/arch/riscv/kernel/dtso.c b/arch/riscv/kernel/dtso.c
new file mode 100644
index 000000000000..fcf7e2e80362
--- /dev/null
+++ b/arch/riscv/kernel/dtso.c
@@ -0,0 +1,33 @@ 
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2023 Christoph Muellner <christoph.muellner@vrull.eu>
+ */
+
+#include <linux/export.h>
+#include <linux/prctl.h>
+#include <asm/dtso.h>
+
+int riscv_set_memory_consistency_model(unsigned long arg)
+{
+	switch (arg) {
+	case PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO:
+		dtso_disable();
+		break;
+	case PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO:
+		if (!has_dtso())
+			return -EINVAL;
+		dtso_enable();
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int riscv_get_memory_consistency_model(void)
+{
+	if (has_dtso() && dtso_is_enabled())
+		return PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO;
+	return PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO;
+}
diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h
index 579662731eaa..20264bdc3092 100644
--- a/include/uapi/linux/prctl.h
+++ b/include/uapi/linux/prctl.h
@@ -308,5 +308,7 @@  struct prctl_mm_map {
 
 #define PR_SET_MEMORY_CONSISTENCY_MODEL		71
 #define PR_GET_MEMORY_CONSISTENCY_MODEL		72
+# define PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO	1
+# define PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO	2
 
 #endif /* _LINUX_PRCTL_H */