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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id q18-20020a1709060e5200b00992f2befcbcsm1709930eji.180.2023.11.23.23.22.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 23:22:12 -0800 (PST) From: Christoph Muellner To: linux-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Albert Ou , Andrew Morton , Shuah Khan , Jonathan Corbet , Anup Patel , Philipp Tomsich , Andrew Jones , Guo Ren , Daniel Henrique Barboza , Conor Dooley , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Alan Stern , Andrea Parri , Will Deacon , Daniel Lustig , Peter Zijlstra Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [RFC PATCH 4/5] RISC-V: Implement prctl call to set/get the memory consistency model Date: Fri, 24 Nov 2023 08:21:41 +0100 Message-ID: <20231124072142.2786653-5-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231124072142.2786653-1-christoph.muellner@vrull.eu> References: <20231124072142.2786653-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231123_232215_960521_11DCE8BF X-CRM114-Status: GOOD ( 21.48 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Christoph Müllner We can use the PR_{S,G}ET_MEMORY_CONSISTENCY_MODEL prctl calls to change the memory consistency model at run-time if we have Ssdtso. This patch registers RISCV_WMO and RISCV_TSO as valid arguments for these prctl calls and implements the glue code to switch between these. Signed-off-by: Christoph Müllner --- .../mm/dynamic-memory-consistency-model.rst | 18 ++++++++++ arch/riscv/include/asm/processor.h | 7 ++++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/dtso.c | 33 +++++++++++++++++++ include/uapi/linux/prctl.h | 2 ++ 5 files changed, 61 insertions(+) create mode 100644 arch/riscv/kernel/dtso.c diff --git a/Documentation/mm/dynamic-memory-consistency-model.rst b/Documentation/mm/dynamic-memory-consistency-model.rst index 21675b41ec84..4a6107a4b71f 100644 --- a/Documentation/mm/dynamic-memory-consistency-model.rst +++ b/Documentation/mm/dynamic-memory-consistency-model.rst @@ -56,3 +56,21 @@ Two prctl calls are defined to get/set the active memory consistency model: to the given model. If the architecture does not support dynamic memory consistency models or does not support the provided model, then -1 is returned, and errno is set to EINVAL. + +Supported memory consistency models +=================================== + +This section defines the memory consistency models which are supported +by the prctl interface. + +RISC-V +------ + +RISC-V uses RVWMO (RISC-V weak memory ordering) as default memory consistency +model. TSO (total store ordering) is another specified model and provides +additional ordering guarantees. Switching from RVWMO to TSO (and back) is +possible when the Ssdtso extension is available. + +* :c:macro:`PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO`: RISC-V weak memory ordering (default). + +* :c:macro:`PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO`: RISC-V total store ordering. diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 79cc5e6377b8..b0c19ddb2cfb 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -146,6 +146,13 @@ extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val); #define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr)) #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) +#ifdef CONFIG_RISCV_ISA_SSDTSO +#define SET_MEMORY_CONSISTENCY_MODEL(arg) dtso_set_memory_ordering(arg) +#define GET_MEMORY_CONSISTENCY_MODEL() dtso_get_memory_ordering() +extern int dtso_set_memory_consistency_model(unsigned long arg); +extern int dtso_get_memory_consistency_model(void); +#endif /* CONIG_RISCV_ISA_SSDTSO */ + #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_PROCESSOR_H */ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index fee22a3d1b53..17cf74ac8e21 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -63,6 +63,7 @@ obj-$(CONFIG_MMU) += vdso.o vdso/ obj-$(CONFIG_RISCV_MISALIGNED) += traps_misaligned.o obj-$(CONFIG_FPU) += fpu.o obj-$(CONFIG_RISCV_ISA_V) += vector.o +obj-$(CONFIG_RISCV_ISA_SSDTSO) += dtso.o obj-$(CONFIG_SMP) += smpboot.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP) += cpu_ops.o diff --git a/arch/riscv/kernel/dtso.c b/arch/riscv/kernel/dtso.c new file mode 100644 index 000000000000..fcf7e2e80362 --- /dev/null +++ b/arch/riscv/kernel/dtso.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2023 Christoph Muellner + */ + +#include +#include +#include + +int riscv_set_memory_consistency_model(unsigned long arg) +{ + switch (arg) { + case PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO: + dtso_disable(); + break; + case PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO: + if (!has_dtso()) + return -EINVAL; + dtso_enable(); + break; + default: + return -EINVAL; + } + + return 0; +} + +int riscv_get_memory_consistency_model(void) +{ + if (has_dtso() && dtso_is_enabled()) + return PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO; + return PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO; +} diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h index 579662731eaa..20264bdc3092 100644 --- a/include/uapi/linux/prctl.h +++ b/include/uapi/linux/prctl.h @@ -308,5 +308,7 @@ struct prctl_mm_map { #define PR_SET_MEMORY_CONSISTENCY_MODEL 71 #define PR_GET_MEMORY_CONSISTENCY_MODEL 72 +# define PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO 1 +# define PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO 2 #endif /* _LINUX_PRCTL_H */