| Message ID | 20231201121410.95298-7-jeeheng.sia@starfivetech.com (mailing list archive) |
|---|---|
| State | Deferred |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | Initial device tree support for StarFive JH8100 SoC | expand |
Hello Sia, Does the dubhe-80 cores actually support vector? Or vector support doesn't exist on actual silicon? Best regards, Shengyu > Add initial device tree for the StarFive JH8100 RISC-V SoC. > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > --- > arch/riscv/boot/dts/starfive/Makefile | 2 + > arch/riscv/boot/dts/starfive/jh8100-evb.dts | 28 ++ > arch/riscv/boot/dts/starfive/jh8100.dtsi | 378 ++++++++++++++++++++ > 3 files changed, 408 insertions(+) > create mode 100644 arch/riscv/boot/dts/starfive/jh8100-evb.dts > create mode 100644 arch/riscv/boot/dts/starfive/jh8100.dtsi > > diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile > index 0141504c0f5c..ef5c7331c7ec 100644 > --- a/arch/riscv/boot/dts/starfive/Makefile > +++ b/arch/riscv/boot/dts/starfive/Makefile > @@ -10,3 +10,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb > > dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb > dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb > + > +dtb-$(CONFIG_ARCH_STARFIVE) += jh8100-evb.dtb > diff --git a/arch/riscv/boot/dts/starfive/jh8100-evb.dts b/arch/riscv/boot/dts/starfive/jh8100-evb.dts > new file mode 100644 > index 000000000000..c16bc25d8988 > --- /dev/null > +++ b/arch/riscv/boot/dts/starfive/jh8100-evb.dts > @@ -0,0 +1,28 @@ > +// SPDX-License-Identifier: GPL-2.0 OR MIT > +/* > + * Copyright (c) 2021-2023 StarFive Technology Co., Ltd. > + */ > + > +#include "jh8100.dtsi" > + > +/ { > + model = "StarFive JH8100 EVB"; > + compatible = "starfive,jh8100-evb", "starfive,jh8100"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + memory@40000000 { > + device_type = "memory"; > + reg = <0x0 0x40000000 0x2 0x00000000>; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > diff --git a/arch/riscv/boot/dts/starfive/jh8100.dtsi b/arch/riscv/boot/dts/starfive/jh8100.dtsi > new file mode 100644 > index 000000000000..f26aff5c1ddf > --- /dev/null > +++ b/arch/riscv/boot/dts/starfive/jh8100.dtsi > @@ -0,0 +1,378 @@ > +// SPDX-License-Identifier: GPL-2.0 OR MIT > +/* > + * Copyright (c) 2021-2023 StarFive Technology Co., Ltd. > + */ > + > +/dts-v1/; > + > +/ { > + compatible = "starfive,jh8100"; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + timebase-frequency = <4000000>; > + > + cpu0: cpu@0 { > + compatible = "starfive,dubhe-80", "riscv"; > + capacity-dmips-mhz = <768>; > + d-cache-block-size = <64>; > + d-cache-sets = <512>; > + d-cache-size = <32768>; > + d-tlb-sets = <1>; > + d-tlb-size = <48>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <512>; > + i-cache-size = <32768>; > + i-tlb-sets = <1>; > + i-tlb-size = <48>; > + mmu-type = "riscv,sv48"; > + next-level-cache = <&l2c0>; > + reg = <0x0>; > + riscv,isa = "rv64imafdch"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", > + "zicsr", "zifencei", "zihintpause", "zihpm", > + "zba", "zbb", "zbs", "sscofpmf"; > + tlb-split; > + > + cpu0_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + cpu1: cpu@1 { > + compatible = "starfive,dubhe-80", "riscv"; > + capacity-dmips-mhz = <768>; > + d-cache-block-size = <64>; > + d-cache-sets = <512>; > + d-cache-size = <32768>; > + d-tlb-sets = <1>; > + d-tlb-size = <48>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <512>; > + i-cache-size = <32768>; > + i-tlb-sets = <1>; > + i-tlb-size = <48>; > + mmu-type = "riscv,sv48"; > + next-level-cache = <&l2c1>; > + reg = <0x1>; > + riscv,isa = "rv64imafdch"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", > + "zicsr", "zifencei", "zihintpause", "zihpm", > + "zba", "zbb", "zbs", "sscofpmf"; > + tlb-split; > + > + cpu1_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + cpu2: cpu@2 { > + compatible = "starfive,dubhe-90", "riscv"; > + capacity-dmips-mhz = <1024>; > + d-cache-block-size = <64>; > + d-cache-sets = <1024>; > + d-cache-size = <65536>; > + d-tlb-sets = <1>; > + d-tlb-size = <48>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <1024>; > + i-cache-size = <65536>; > + i-tlb-sets = <1>; > + i-tlb-size = <48>; > + mmu-type = "riscv,sv48"; > + next-level-cache = <&l2c2>; > + reg = <0x2>; > + riscv,isa = "rv64imafdch"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", > + "zicsr", "zifencei", "zihintpause", "zihpm", > + "zba", "zbb", "zbs", "sscofpmf"; > + tlb-split; > + > + cpu2_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + cpu3: cpu@3 { > + compatible = "starfive,dubhe-90", "riscv"; > + capacity-dmips-mhz = <1024>; > + d-cache-block-size = <64>; > + d-cache-sets = <1024>; > + d-cache-size = <65536>; > + d-tlb-sets = <1>; > + d-tlb-size = <48>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <1024>; > + i-cache-size = <65536>; > + i-tlb-sets = <1>; > + i-tlb-size = <48>; > + mmu-type = "riscv,sv48"; > + next-level-cache = <&l2c2>; > + reg = <0x3>; > + riscv,isa = "rv64imafdch"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", > + "zicsr", "zifencei", "zihintpause", "zihpm", > + "zba", "zbb", "zbs", "sscofpmf"; > + tlb-split; > + > + cpu3_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + cpu4: cpu@4 { > + compatible = "starfive,dubhe-90", "riscv"; > + capacity-dmips-mhz = <1024>; > + d-cache-block-size = <64>; > + d-cache-sets = <1024>; > + d-cache-size = <65536>; > + d-tlb-sets = <1>; > + d-tlb-size = <48>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <1024>; > + i-cache-size = <65536>; > + i-tlb-sets = <1>; > + i-tlb-size = <48>; > + mmu-type = "riscv,sv48"; > + next-level-cache = <&l2c2>; > + reg = <0x4>; > + riscv,isa = "rv64imafdch"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", > + "zicsr", "zifencei", "zihintpause", "zihpm", > + "zba", "zbb", "zbs", "sscofpmf"; > + tlb-split; > + > + cpu4_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + cpu5: cpu@5 { > + compatible = "starfive,dubhe-90", "riscv"; > + capacity-dmips-mhz = <1024>; > + d-cache-block-size = <64>; > + d-cache-sets = <1024>; > + d-cache-size = <65536>; > + d-tlb-sets = <1>; > + d-tlb-size = <48>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <1024>; > + i-cache-size = <65536>; > + i-tlb-sets = <1>; > + i-tlb-size = <48>; > + mmu-type = "riscv,sv48"; > + next-level-cache = <&l2c2>; > + reg = <0x5>; > + riscv,isa = "rv64imafdch"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", > + "zicsr", "zifencei", "zihintpause", "zihpm", > + "zba", "zbb", "zbs", "sscofpmf"; > + tlb-split; > + > + cpu5_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #interrupt-cells = <1>; > + }; > + }; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&cpu1>; > + }; > + }; > + > + cluster2 { > + core0 { > + cpu = <&cpu2>; > + }; > + > + core1 { > + cpu = <&cpu3>; > + }; > + > + core2 { > + cpu = <&cpu4>; > + }; > + > + core3 { > + cpu = <&cpu5>; > + }; > + }; > + }; > + > + l2c0: cache-controller-0 { > + compatible = "cache"; > + cache-block-size = <64>; > + cache-level = <2>; > + cache-sets = <512>; > + cache-size = <0x40000>; > + cache-unified; > + next-level-cache = <&l3_cache>; > + }; > + > + l2c1: cache-controller-1 { > + compatible = "cache"; > + cache-block-size = <64>; > + cache-level = <2>; > + cache-sets = <512>; > + cache-size = <0x40000>; > + cache-unified; > + next-level-cache = <&l3_cache>; > + }; > + > + l2c2: cache-controller-2{ > + compatible = "cache"; > + cache-block-size = <64>; > + cache-level = <2>; > + cache-sets = <4096>; > + cache-size = <0x200000>; > + cache-unified; > + next-level-cache = <&l3_cache>; > + }; > + > + l3_cache: cache-controller-3 { > + compatible = "cache"; > + cache-block-size = <64>; > + cache-level = <3>; > + cache-sets = <8192>; > + cache-size = <0x400000>; > + cache-unified; > + }; > + }; > + > + clk_uart: clk-uart { > + compatible = "fixed-clock"; /* Initial clock handler for UART */ > + #clock-cells = <0>; > + clock-frequency = <24000000>; > + }; > + > + soc { > + compatible = "simple-bus"; > + interrupt-parent = <&plic>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + clint: clint@2000000 { > + compatible = "starfive,jh8100-clint", "sifive,clint0"; > + reg = <0x0 0x2000000 0x0 0x10000>; > + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, > + <&cpu1_intc 3>, <&cpu1_intc 7>, > + <&cpu2_intc 3>, <&cpu2_intc 7>, > + <&cpu3_intc 3>, <&cpu3_intc 7>, > + <&cpu4_intc 3>, <&cpu4_intc 7>, > + <&cpu5_intc 3>, <&cpu5_intc 7>; > + }; > + > + plic: interrupt-controller@c000000 { > + #interrupt-cells = <1>; > + #address-cells = <0>; > + compatible = "starfive,jh8100-plic", "sifive,plic-1.0.0"; > + reg = <0x0 0x0c000000 0x0 0x4000000>; > + riscv,ndev = <200>; > + interrupt-controller; > + interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>, > + <&cpu0_intc 9>, <&cpu1_intc 9>, > + <&cpu2_intc 11>, <&cpu3_intc 11>, > + <&cpu4_intc 11>, <&cpu5_intc 11>, > + <&cpu2_intc 9>, <&cpu3_intc 9>, > + <&cpu4_intc 9>, <&cpu5_intc 9>; > + }; > + > + uart0: serial@12160000 { > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > + reg = <0x0 0x12160000 0x0 0x10000>; > + clock-names = "uart_clk", "pclk"; > + clocks = <&clk_uart>, <&clk_uart>; > + interrupts = <67>; > + status = "disabled"; > + }; > + > + uart1: serial@12170000 { > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > + reg = <0x0 0x12170000 0x0 0x10000>; > + clock-names = "uart_clk", "pclk"; > + clocks = <&clk_uart>, <&clk_uart>; > + interrupts = <68>; > + status = "disabled"; > + }; > + > + uart2: serial@12180000 { > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > + reg = <0x0 0x12180000 0x0 0x10000>; > + clock-names = "uart_clk", "pclk"; > + clocks = <&clk_uart>, <&clk_uart>; > + interrupts = <69>; > + status = "disabled"; > + }; > + > + uart3: serial@12190000 { > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > + reg = <0x0 0x12190000 0x0 0x10000>; > + clock-names = "uart_clk", "pclk"; > + clocks = <&clk_uart>, <&clk_uart>; > + interrupts = <70>; > + status = "disabled"; > + }; > + > + uart4: serial@121a0000 { > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > + reg = <0x0 0x121a0000 0x0 0x10000>; > + clock-names = "uart_clk", "pclk"; > + clocks = <&clk_uart>, <&clk_uart>; > + interrupts = <71>; > + status = "disabled"; > + }; > + > + uart5: serial@127d0000 { > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > + reg = <0x0 0x127d0000 0x0 0x10000>; > + clock-names = "uart_clk", "pclk"; > + clocks = <&clk_uart>, <&clk_uart>; > + interrupts = <72>; > + status = "disabled"; > + }; > + > + uart6: serial@127e0000 { > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > + reg = <0x0 0x127e0000 0x0 0x10000>; > + clock-names = "uart_clk", "pclk"; > + clocks = <&clk_uart>, <&clk_uart>; > + interrupts = <73>; > + status = "disabled"; > + }; > + }; > +};
Sia Jee Heng wrote: > Add initial device tree for the StarFive JH8100 RISC-V SoC. > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> Looks good to me, thanks. Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> -----Original Message----- > From: Shengyu Qu <wiagn233@outlook.com> > Sent: Friday, December 8, 2023 8:09 PM > To: JeeHeng Sia <jeeheng.sia@starfivetech.com>; kernel@esmil.dk; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; > krzk@kernel.org; conor+dt@kernel.org; paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; > daniel.lezcano@linaro.org; tglx@linutronix.de; conor@kernel.org; anup@brainfault.org; gregkh@linuxfoundation.org; > jirislaby@kernel.org; michal.simek@amd.com; Michael Zhu <michael.zhu@starfivetech.com>; drew@beagleboard.org > Cc: wiagn233@outlook.com; devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Leyfoon Tan > <leyfoon.tan@starfivetech.com> > Subject: Re: [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree > > Hello Sia, Hi Shengyu > > Does the dubhe-80 cores actually support vector? Or vector support > > doesn't exist on actual silicon? We don't have a use case for vector application in JH8100 > > Best regards, > > Shengyu > > > Add initial device tree for the StarFive JH8100 RISC-V SoC. > > > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > > --- > > arch/riscv/boot/dts/starfive/Makefile | 2 + > > arch/riscv/boot/dts/starfive/jh8100-evb.dts | 28 ++ > > arch/riscv/boot/dts/starfive/jh8100.dtsi | 378 ++++++++++++++++++++ > > 3 files changed, 408 insertions(+) > > create mode 100644 arch/riscv/boot/dts/starfive/jh8100-evb.dts > > create mode 100644 arch/riscv/boot/dts/starfive/jh8100.dtsi > > > > diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile > > index 0141504c0f5c..ef5c7331c7ec 100644 > > --- a/arch/riscv/boot/dts/starfive/Makefile > > +++ b/arch/riscv/boot/dts/starfive/Makefile > > @@ -10,3 +10,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb > > > > dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb > > dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb > > + > > +dtb-$(CONFIG_ARCH_STARFIVE) += jh8100-evb.dtb > > diff --git a/arch/riscv/boot/dts/starfive/jh8100-evb.dts b/arch/riscv/boot/dts/starfive/jh8100-evb.dts > > new file mode 100644 > > index 000000000000..c16bc25d8988 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/starfive/jh8100-evb.dts > > @@ -0,0 +1,28 @@ > > +// SPDX-License-Identifier: GPL-2.0 OR MIT > > +/* > > + * Copyright (c) 2021-2023 StarFive Technology Co., Ltd. > > + */ > > + > > +#include "jh8100.dtsi" > > + > > +/ { > > + model = "StarFive JH8100 EVB"; > > + compatible = "starfive,jh8100-evb", "starfive,jh8100"; > > + > > + aliases { > > + serial0 = &uart0; > > + }; > > + > > + chosen { > > + stdout-path = "serial0:115200n8"; > > + }; > > + > > + memory@40000000 { > > + device_type = "memory"; > > + reg = <0x0 0x40000000 0x2 0x00000000>; > > + }; > > +}; > > + > > +&uart0 { > > + status = "okay"; > > +}; > > diff --git a/arch/riscv/boot/dts/starfive/jh8100.dtsi b/arch/riscv/boot/dts/starfive/jh8100.dtsi > > new file mode 100644 > > index 000000000000..f26aff5c1ddf > > --- /dev/null > > +++ b/arch/riscv/boot/dts/starfive/jh8100.dtsi > > @@ -0,0 +1,378 @@ > > +// SPDX-License-Identifier: GPL-2.0 OR MIT > > +/* > > + * Copyright (c) 2021-2023 StarFive Technology Co., Ltd. > > + */ > > + > > +/dts-v1/; > > + > > +/ { > > + compatible = "starfive,jh8100"; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + timebase-frequency = <4000000>; > > + > > + cpu0: cpu@0 { > > + compatible = "starfive,dubhe-80", "riscv"; > > + capacity-dmips-mhz = <768>; > > + d-cache-block-size = <64>; > > + d-cache-sets = <512>; > > + d-cache-size = <32768>; > > + d-tlb-sets = <1>; > > + d-tlb-size = <48>; > > + device_type = "cpu"; > > + i-cache-block-size = <64>; > > + i-cache-sets = <512>; > > + i-cache-size = <32768>; > > + i-tlb-sets = <1>; > > + i-tlb-size = <48>; > > + mmu-type = "riscv,sv48"; > > + next-level-cache = <&l2c0>; > > + reg = <0x0>; > > + riscv,isa = "rv64imafdch"; > > + riscv,isa-base = "rv64i"; > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", > > + "zicsr", "zifencei", "zihintpause", "zihpm", > > + "zba", "zbb", "zbs", "sscofpmf"; > > + tlb-split; > > + > > + cpu0_intc: interrupt-controller { > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + }; > > + }; > > + > > + cpu1: cpu@1 { > > + compatible = "starfive,dubhe-80", "riscv"; > > + capacity-dmips-mhz = <768>; > > + d-cache-block-size = <64>; > > + d-cache-sets = <512>; > > + d-cache-size = <32768>; > > + d-tlb-sets = <1>; > > + d-tlb-size = <48>; > > + device_type = "cpu"; > > + i-cache-block-size = <64>; > > + i-cache-sets = <512>; > > + i-cache-size = <32768>; > > + i-tlb-sets = <1>; > > + i-tlb-size = <48>; > > + mmu-type = "riscv,sv48"; > > + next-level-cache = <&l2c1>; > > + reg = <0x1>; > > + riscv,isa = "rv64imafdch"; > > + riscv,isa-base = "rv64i"; > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", > > + "zicsr", "zifencei", "zihintpause", "zihpm", > > + "zba", "zbb", "zbs", "sscofpmf"; > > + tlb-split; > > + > > + cpu1_intc: interrupt-controller { > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + }; > > + }; > > + > > + cpu2: cpu@2 { > > + compatible = "starfive,dubhe-90", "riscv"; > > + capacity-dmips-mhz = <1024>; > > + d-cache-block-size = <64>; > > + d-cache-sets = <1024>; > > + d-cache-size = <65536>; > > + d-tlb-sets = <1>; > > + d-tlb-size = <48>; > > + device_type = "cpu"; > > + i-cache-block-size = <64>; > > + i-cache-sets = <1024>; > > + i-cache-size = <65536>; > > + i-tlb-sets = <1>; > > + i-tlb-size = <48>; > > + mmu-type = "riscv,sv48"; > > + next-level-cache = <&l2c2>; > > + reg = <0x2>; > > + riscv,isa = "rv64imafdch"; > > + riscv,isa-base = "rv64i"; > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", > > + "zicsr", "zifencei", "zihintpause", "zihpm", > > + "zba", "zbb", "zbs", "sscofpmf"; > > + tlb-split; > > + > > + cpu2_intc: interrupt-controller { > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + }; > > + }; > > + > > + cpu3: cpu@3 { > > + compatible = "starfive,dubhe-90", "riscv"; > > + capacity-dmips-mhz = <1024>; > > + d-cache-block-size = <64>; > > + d-cache-sets = <1024>; > > + d-cache-size = <65536>; > > + d-tlb-sets = <1>; > > + d-tlb-size = <48>; > > + device_type = "cpu"; > > + i-cache-block-size = <64>; > > + i-cache-sets = <1024>; > > + i-cache-size = <65536>; > > + i-tlb-sets = <1>; > > + i-tlb-size = <48>; > > + mmu-type = "riscv,sv48"; > > + next-level-cache = <&l2c2>; > > + reg = <0x3>; > > + riscv,isa = "rv64imafdch"; > > + riscv,isa-base = "rv64i"; > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", > > + "zicsr", "zifencei", "zihintpause", "zihpm", > > + "zba", "zbb", "zbs", "sscofpmf"; > > + tlb-split; > > + > > + cpu3_intc: interrupt-controller { > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + }; > > + }; > > + > > + cpu4: cpu@4 { > > + compatible = "starfive,dubhe-90", "riscv"; > > + capacity-dmips-mhz = <1024>; > > + d-cache-block-size = <64>; > > + d-cache-sets = <1024>; > > + d-cache-size = <65536>; > > + d-tlb-sets = <1>; > > + d-tlb-size = <48>; > > + device_type = "cpu"; > > + i-cache-block-size = <64>; > > + i-cache-sets = <1024>; > > + i-cache-size = <65536>; > > + i-tlb-sets = <1>; > > + i-tlb-size = <48>; > > + mmu-type = "riscv,sv48"; > > + next-level-cache = <&l2c2>; > > + reg = <0x4>; > > + riscv,isa = "rv64imafdch"; > > + riscv,isa-base = "rv64i"; > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", > > + "zicsr", "zifencei", "zihintpause", "zihpm", > > + "zba", "zbb", "zbs", "sscofpmf"; > > + tlb-split; > > + > > + cpu4_intc: interrupt-controller { > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + }; > > + }; > > + > > + cpu5: cpu@5 { > > + compatible = "starfive,dubhe-90", "riscv"; > > + capacity-dmips-mhz = <1024>; > > + d-cache-block-size = <64>; > > + d-cache-sets = <1024>; > > + d-cache-size = <65536>; > > + d-tlb-sets = <1>; > > + d-tlb-size = <48>; > > + device_type = "cpu"; > > + i-cache-block-size = <64>; > > + i-cache-sets = <1024>; > > + i-cache-size = <65536>; > > + i-tlb-sets = <1>; > > + i-tlb-size = <48>; > > + mmu-type = "riscv,sv48"; > > + next-level-cache = <&l2c2>; > > + reg = <0x5>; > > + riscv,isa = "rv64imafdch"; > > + riscv,isa-base = "rv64i"; > > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", > > + "zicsr", "zifencei", "zihintpause", "zihpm", > > + "zba", "zbb", "zbs", "sscofpmf"; > > + tlb-split; > > + > > + cpu5_intc: interrupt-controller { > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + #interrupt-cells = <1>; > > + }; > > + }; > > + > > + cpu-map { > > + cluster0 { > > + core0 { > > + cpu = <&cpu0>; > > + }; > > + }; > > + > > + cluster1 { > > + core0 { > > + cpu = <&cpu1>; > > + }; > > + }; > > + > > + cluster2 { > > + core0 { > > + cpu = <&cpu2>; > > + }; > > + > > + core1 { > > + cpu = <&cpu3>; > > + }; > > + > > + core2 { > > + cpu = <&cpu4>; > > + }; > > + > > + core3 { > > + cpu = <&cpu5>; > > + }; > > + }; > > + }; > > + > > + l2c0: cache-controller-0 { > > + compatible = "cache"; > > + cache-block-size = <64>; > > + cache-level = <2>; > > + cache-sets = <512>; > > + cache-size = <0x40000>; > > + cache-unified; > > + next-level-cache = <&l3_cache>; > > + }; > > + > > + l2c1: cache-controller-1 { > > + compatible = "cache"; > > + cache-block-size = <64>; > > + cache-level = <2>; > > + cache-sets = <512>; > > + cache-size = <0x40000>; > > + cache-unified; > > + next-level-cache = <&l3_cache>; > > + }; > > + > > + l2c2: cache-controller-2{ > > + compatible = "cache"; > > + cache-block-size = <64>; > > + cache-level = <2>; > > + cache-sets = <4096>; > > + cache-size = <0x200000>; > > + cache-unified; > > + next-level-cache = <&l3_cache>; > > + }; > > + > > + l3_cache: cache-controller-3 { > > + compatible = "cache"; > > + cache-block-size = <64>; > > + cache-level = <3>; > > + cache-sets = <8192>; > > + cache-size = <0x400000>; > > + cache-unified; > > + }; > > + }; > > + > > + clk_uart: clk-uart { > > + compatible = "fixed-clock"; /* Initial clock handler for UART */ > > + #clock-cells = <0>; > > + clock-frequency = <24000000>; > > + }; > > + > > + soc { > > + compatible = "simple-bus"; > > + interrupt-parent = <&plic>; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + > > + clint: clint@2000000 { > > + compatible = "starfive,jh8100-clint", "sifive,clint0"; > > + reg = <0x0 0x2000000 0x0 0x10000>; > > + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, > > + <&cpu1_intc 3>, <&cpu1_intc 7>, > > + <&cpu2_intc 3>, <&cpu2_intc 7>, > > + <&cpu3_intc 3>, <&cpu3_intc 7>, > > + <&cpu4_intc 3>, <&cpu4_intc 7>, > > + <&cpu5_intc 3>, <&cpu5_intc 7>; > > + }; > > + > > + plic: interrupt-controller@c000000 { > > + #interrupt-cells = <1>; > > + #address-cells = <0>; > > + compatible = "starfive,jh8100-plic", "sifive,plic-1.0.0"; > > + reg = <0x0 0x0c000000 0x0 0x4000000>; > > + riscv,ndev = <200>; > > + interrupt-controller; > > + interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>, > > + <&cpu0_intc 9>, <&cpu1_intc 9>, > > + <&cpu2_intc 11>, <&cpu3_intc 11>, > > + <&cpu4_intc 11>, <&cpu5_intc 11>, > > + <&cpu2_intc 9>, <&cpu3_intc 9>, > > + <&cpu4_intc 9>, <&cpu5_intc 9>; > > + }; > > + > > + uart0: serial@12160000 { > > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > > + reg = <0x0 0x12160000 0x0 0x10000>; > > + clock-names = "uart_clk", "pclk"; > > + clocks = <&clk_uart>, <&clk_uart>; > > + interrupts = <67>; > > + status = "disabled"; > > + }; > > + > > + uart1: serial@12170000 { > > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > > + reg = <0x0 0x12170000 0x0 0x10000>; > > + clock-names = "uart_clk", "pclk"; > > + clocks = <&clk_uart>, <&clk_uart>; > > + interrupts = <68>; > > + status = "disabled"; > > + }; > > + > > + uart2: serial@12180000 { > > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > > + reg = <0x0 0x12180000 0x0 0x10000>; > > + clock-names = "uart_clk", "pclk"; > > + clocks = <&clk_uart>, <&clk_uart>; > > + interrupts = <69>; > > + status = "disabled"; > > + }; > > + > > + uart3: serial@12190000 { > > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > > + reg = <0x0 0x12190000 0x0 0x10000>; > > + clock-names = "uart_clk", "pclk"; > > + clocks = <&clk_uart>, <&clk_uart>; > > + interrupts = <70>; > > + status = "disabled"; > > + }; > > + > > + uart4: serial@121a0000 { > > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > > + reg = <0x0 0x121a0000 0x0 0x10000>; > > + clock-names = "uart_clk", "pclk"; > > + clocks = <&clk_uart>, <&clk_uart>; > > + interrupts = <71>; > > + status = "disabled"; > > + }; > > + > > + uart5: serial@127d0000 { > > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > > + reg = <0x0 0x127d0000 0x0 0x10000>; > > + clock-names = "uart_clk", "pclk"; > > + clocks = <&clk_uart>, <&clk_uart>; > > + interrupts = <72>; > > + status = "disabled"; > > + }; > > + > > + uart6: serial@127e0000 { > > + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; > > + reg = <0x0 0x127e0000 0x0 0x10000>; > > + clock-names = "uart_clk", "pclk"; > > + clocks = <&clk_uart>, <&clk_uart>; > > + interrupts = <73>; > > + status = "disabled"; > > + }; > > + }; > > +};
On Mon, Dec 11, 2023 at 01:38:06AM +0000, JeeHeng Sia wrote: > > > From: Shengyu Qu <wiagn233@outlook.com> > > Sent: Friday, December 8, 2023 8:09 PM > > Does the dubhe-80 cores actually support vector? Or vector support > > > > doesn't exist on actual silicon? > We don't have a use case for vector application in JH8100 I am sorry, but I am not clear on what this means. Do the CPUs on the JH8100 support vector or not?
> -----Original Message----- > From: Conor Dooley <conor.dooley@microchip.com> > Sent: Monday, December 11, 2023 3:59 PM > To: JeeHeng Sia <jeeheng.sia@starfivetech.com> > Cc: Shengyu Qu <wiagn233@outlook.com>; kernel@esmil.dk; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; > krzk@kernel.org; conor+dt@kernel.org; paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; > daniel.lezcano@linaro.org; tglx@linutronix.de; conor@kernel.org; anup@brainfault.org; gregkh@linuxfoundation.org; > jirislaby@kernel.org; michal.simek@amd.com; Michael Zhu <michael.zhu@starfivetech.com>; drew@beagleboard.org; > devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Leyfoon Tan > <leyfoon.tan@starfivetech.com> > Subject: Re: [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree > > On Mon, Dec 11, 2023 at 01:38:06AM +0000, JeeHeng Sia wrote: > > > > > From: Shengyu Qu <wiagn233@outlook.com> > > > Sent: Friday, December 8, 2023 8:09 PM > > > > Does the dubhe-80 cores actually support vector? Or vector support > > > > > > doesn't exist on actual silicon? > > > We don't have a use case for vector application in JH8100 > > I am sorry, but I am not clear on what this means. Do the CPUs on > the JH8100 support vector or not? The JH8100 CPU does not support vector operation.
On Mon, Dec 11, 2023 at 09:38:03AM +0000, JeeHeng Sia wrote: > > > > -----Original Message----- > > From: Conor Dooley <conor.dooley@microchip.com> > > Sent: Monday, December 11, 2023 3:59 PM > > To: JeeHeng Sia <jeeheng.sia@starfivetech.com> > > Cc: Shengyu Qu <wiagn233@outlook.com>; kernel@esmil.dk; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; > > krzk@kernel.org; conor+dt@kernel.org; paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu; > > daniel.lezcano@linaro.org; tglx@linutronix.de; conor@kernel.org; anup@brainfault.org; gregkh@linuxfoundation.org; > > jirislaby@kernel.org; michal.simek@amd.com; Michael Zhu <michael.zhu@starfivetech.com>; drew@beagleboard.org; > > devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Leyfoon Tan > > <leyfoon.tan@starfivetech.com> > > Subject: Re: [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree > > > > On Mon, Dec 11, 2023 at 01:38:06AM +0000, JeeHeng Sia wrote: > > > > > > > From: Shengyu Qu <wiagn233@outlook.com> > > > > Sent: Friday, December 8, 2023 8:09 PM > > > > > > Does the dubhe-80 cores actually support vector? Or vector support > > > > > > > > doesn't exist on actual silicon? > > > > > We don't have a use case for vector application in JH8100 > > > > I am sorry, but I am not clear on what this means. Do the CPUs on > > the JH8100 support vector or not? > The JH8100 CPU does not support vector operation. Thanks for clarifiying.
Emil Renner Berthing wrote: > Sia Jee Heng wrote: > > Add initial device tree for the StarFive JH8100 RISC-V SoC. > > > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > > Looks good to me, thanks. > > Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> I just learned that this JH8100 is not actually a real SoC yet but just an FPGA implementation, and no indication that that's actually a product that will be mass produced. Hence a lot of details may change before it becomes a real SoC/product people can buy, so let's not add this device tree yet before everything is set in silicon. Please consider my Acked-by abeve revoked. Sia Jee Heng: With that said I still think it's super awesome that you're beginning upstreaming support for your new SoCs early. I wish more SoC vendors would follow your example. /Emil
> -----Original Message----- > From: Emil Renner Berthing <emil.renner.berthing@canonical.com> > Sent: Wednesday, December 13, 2023 8:39 PM > To: Emil Renner Berthing <emil.renner.berthing@canonical.com>; JeeHeng Sia <jeeheng.sia@starfivetech.com>; kernel@esmil.dk; > robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; krzk@kernel.org; conor+dt@kernel.org; paul.walmsley@sifive.com; > palmer@dabbelt.com; aou@eecs.berkeley.edu; daniel.lezcano@linaro.org; tglx@linutronix.de; conor@kernel.org; > anup@brainfault.org; gregkh@linuxfoundation.org; jirislaby@kernel.org; michal.simek@amd.com; Michael Zhu > <michael.zhu@starfivetech.com>; drew@beagleboard.org > Cc: devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Leyfoon Tan > <leyfoon.tan@starfivetech.com> > Subject: Re: [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree > > Emil Renner Berthing wrote: > > Sia Jee Heng wrote: > > > Add initial device tree for the StarFive JH8100 RISC-V SoC. > > > > > > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com> > > > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> > > > > Looks good to me, thanks. > > > > Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > I just learned that this JH8100 is not actually a real SoC yet but just an FPGA > implementation, and no indication that that's actually a product that will be > mass produced. Hence a lot of details may change before it becomes a real > SoC/product people can buy, so let's not add this device tree yet before > everything is set in silicon. > > Please consider my Acked-by abeve revoked. > > Sia Jee Heng: With that said I still think it's super awesome that you're > beginning upstreaming support for your new SoCs early. I wish more SoC vendors > would follow your example. Hi Emil, I am not sure what you mean. We verified on FPGA & Emulator, and the logic is pretty much close to the real silicon. I did mention that in the cover letter as well. I am new to Linux, so I am wondering if there is a Linux upstream guideline mentioning that pre-silicon software is not allowed to upstream? Hope there is an updated Linux upstream guideline that benefit other vendors. > > /Emil
diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile index 0141504c0f5c..ef5c7331c7ec 100644 --- a/arch/riscv/boot/dts/starfive/Makefile +++ b/arch/riscv/boot/dts/starfive/Makefile @@ -10,3 +10,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb + +dtb-$(CONFIG_ARCH_STARFIVE) += jh8100-evb.dtb diff --git a/arch/riscv/boot/dts/starfive/jh8100-evb.dts b/arch/riscv/boot/dts/starfive/jh8100-evb.dts new file mode 100644 index 000000000000..c16bc25d8988 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh8100-evb.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2021-2023 StarFive Technology Co., Ltd. + */ + +#include "jh8100.dtsi" + +/ { + model = "StarFive JH8100 EVB"; + compatible = "starfive,jh8100-evb", "starfive,jh8100"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0x2 0x00000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh8100.dtsi b/arch/riscv/boot/dts/starfive/jh8100.dtsi new file mode 100644 index 000000000000..f26aff5c1ddf --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh8100.dtsi @@ -0,0 +1,378 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2021-2023 StarFive Technology Co., Ltd. + */ + +/dts-v1/; + +/ { + compatible = "starfive,jh8100"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <4000000>; + + cpu0: cpu@0 { + compatible = "starfive,dubhe-80", "riscv"; + capacity-dmips-mhz = <768>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <512>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <48>; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2c0>; + reg = <0x0>; + riscv,isa = "rv64imafdch"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu1: cpu@1 { + compatible = "starfive,dubhe-80", "riscv"; + capacity-dmips-mhz = <768>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <512>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <48>; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2c1>; + reg = <0x1>; + riscv,isa = "rv64imafdch"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu2: cpu@2 { + compatible = "starfive,dubhe-90", "riscv"; + capacity-dmips-mhz = <1024>; + d-cache-block-size = <64>; + d-cache-sets = <1024>; + d-cache-size = <65536>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <1024>; + i-cache-size = <65536>; + i-tlb-sets = <1>; + i-tlb-size = <48>; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2c2>; + reg = <0x2>; + riscv,isa = "rv64imafdch"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu3: cpu@3 { + compatible = "starfive,dubhe-90", "riscv"; + capacity-dmips-mhz = <1024>; + d-cache-block-size = <64>; + d-cache-sets = <1024>; + d-cache-size = <65536>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <1024>; + i-cache-size = <65536>; + i-tlb-sets = <1>; + i-tlb-size = <48>; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2c2>; + reg = <0x3>; + riscv,isa = "rv64imafdch"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu4: cpu@4 { + compatible = "starfive,dubhe-90", "riscv"; + capacity-dmips-mhz = <1024>; + d-cache-block-size = <64>; + d-cache-sets = <1024>; + d-cache-size = <65536>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <1024>; + i-cache-size = <65536>; + i-tlb-sets = <1>; + i-tlb-size = <48>; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2c2>; + reg = <0x4>; + riscv,isa = "rv64imafdch"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu4_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu5: cpu@5 { + compatible = "starfive,dubhe-90", "riscv"; + capacity-dmips-mhz = <1024>; + d-cache-block-size = <64>; + d-cache-sets = <1024>; + d-cache-size = <65536>; + d-tlb-sets = <1>; + d-tlb-size = <48>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <1024>; + i-cache-size = <65536>; + i-tlb-sets = <1>; + i-tlb-size = <48>; + mmu-type = "riscv,sv48"; + next-level-cache = <&l2c2>; + reg = <0x5>; + riscv,isa = "rv64imafdch"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu5_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu1>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu2>; + }; + + core1 { + cpu = <&cpu3>; + }; + + core2 { + cpu = <&cpu4>; + }; + + core3 { + cpu = <&cpu5>; + }; + }; + }; + + l2c0: cache-controller-0 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <512>; + cache-size = <0x40000>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2c1: cache-controller-1 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <512>; + cache-size = <0x40000>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2c2: cache-controller-2{ + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <4096>; + cache-size = <0x200000>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l3_cache: cache-controller-3 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <3>; + cache-sets = <8192>; + cache-size = <0x400000>; + cache-unified; + }; + }; + + clk_uart: clk-uart { + compatible = "fixed-clock"; /* Initial clock handler for UART */ + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clint: clint@2000000 { + compatible = "starfive,jh8100-clint", "sifive,clint0"; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>, + <&cpu5_intc 3>, <&cpu5_intc 7>; + }; + + plic: interrupt-controller@c000000 { + #interrupt-cells = <1>; + #address-cells = <0>; + compatible = "starfive,jh8100-plic", "sifive,plic-1.0.0"; + reg = <0x0 0x0c000000 0x0 0x4000000>; + riscv,ndev = <200>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>, + <&cpu0_intc 9>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu3_intc 11>, + <&cpu4_intc 11>, <&cpu5_intc 11>, + <&cpu2_intc 9>, <&cpu3_intc 9>, + <&cpu4_intc 9>, <&cpu5_intc 9>; + }; + + uart0: serial@12160000 { + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; + reg = <0x0 0x12160000 0x0 0x10000>; + clock-names = "uart_clk", "pclk"; + clocks = <&clk_uart>, <&clk_uart>; + interrupts = <67>; + status = "disabled"; + }; + + uart1: serial@12170000 { + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; + reg = <0x0 0x12170000 0x0 0x10000>; + clock-names = "uart_clk", "pclk"; + clocks = <&clk_uart>, <&clk_uart>; + interrupts = <68>; + status = "disabled"; + }; + + uart2: serial@12180000 { + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; + reg = <0x0 0x12180000 0x0 0x10000>; + clock-names = "uart_clk", "pclk"; + clocks = <&clk_uart>, <&clk_uart>; + interrupts = <69>; + status = "disabled"; + }; + + uart3: serial@12190000 { + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; + reg = <0x0 0x12190000 0x0 0x10000>; + clock-names = "uart_clk", "pclk"; + clocks = <&clk_uart>, <&clk_uart>; + interrupts = <70>; + status = "disabled"; + }; + + uart4: serial@121a0000 { + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; + reg = <0x0 0x121a0000 0x0 0x10000>; + clock-names = "uart_clk", "pclk"; + clocks = <&clk_uart>, <&clk_uart>; + interrupts = <71>; + status = "disabled"; + }; + + uart5: serial@127d0000 { + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; + reg = <0x0 0x127d0000 0x0 0x10000>; + clock-names = "uart_clk", "pclk"; + clocks = <&clk_uart>, <&clk_uart>; + interrupts = <72>; + status = "disabled"; + }; + + uart6: serial@127e0000 { + compatible = "starfive,jh8100-uart", "cdns,uart-r1p8"; + reg = <0x0 0x127e0000 0x0 0x10000>; + clock-names = "uart_clk", "pclk"; + clocks = <&clk_uart>, <&clk_uart>; + interrupts = <73>; + status = "disabled"; + }; + }; +};