new file mode 100644
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh8100-aoncrg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH8100 Always-On Clock and Reset Generator
+
+maintainers:
+ - Sia Jee Heng <jeeheng.sia@starfivetech.com>
+
+properties:
+ compatible:
+ const: starfive,jh8100-aoncrg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Main Oscillator (24 MHz)
+ - description: GMAC0 RMII func
+ - description: GMAC0 RGMII func
+ - description: AON 125MHz clock
+ - description: AON 2000MHz clock
+ - description: AON 200MHz clock
+ - description: AON 667MHz clock
+ - description: RTC clock
+
+ clock-names:
+ items:
+ - const: clk_osc
+ - const: clk_gmac0_rmii_func
+ - const: clk_gmac0_rgmii_func
+ - const: clk_aon125
+ - const: clk_aon2000
+ - const: clk_aon200
+ - const: clk_aon667
+ - const: clk_rtc
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jh8100-crg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/starfive-jh8100-crg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/starfive,jh8100-crg.h>
+
+ clock-controller@1f310000 {
+ compatible = "starfive,jh8100-aoncrg";
+ reg = <0x1f310000 0x10000>;
+ clocks = <&clk_osc>, <&clk_gmac0_rmii_func>,
+ <&clk_gmac0_rgmii_func>, <&clk_aon125>,
+ <&clk_aon2000>, <&clk_aon200>,
+ <&clk_aon667>, <&clk_rtc>;
+ clock-names = "clk_osc", "clk_gmac0_rmii_func", "clk_gmac0_rgmii_func",
+ "clk_aon125", "clk_aon2000", "clk_aon200",
+ "clk_aon667", "clk_rtc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
@@ -358,4 +358,73 @@
#define SYSCRG_SW_CLK_VDEC_ICG_EN 9
#define SYSCRG_SW_CLK_END 10
+
+/* AONCRG_CLK */
+#define AONCRG_CLK_GMAC0_RMII_REFIN 0
+#define AONCRG_CLK_GMAC0_RGMII_RXIN 1
+#define AONCRG_CLK_GMAC0_GTXCLK 2
+#define AONCRG_CLK_AON_1000 3
+#define AONCRG_CLK_AON_400 4
+#define AONCRG_CLK_AON_400_POSTOSC 5
+#define AONCRG_CLK_AON_500 6
+#define AONCRG_CLK_AON_500_POSTOSC 7
+#define AONCRG_CLK_XSPI_PHY 8
+#define AONCRG_CLK_AON_100 9
+#define AONCRG_CLK_AON_100_POSTOSC 10
+#define AONCRG_CLK_AON_50_POSTOSC 11
+#define AONCRG_CLK_DDR50_POSTOCC_ICG 12
+#define AONCRG_CLK_DDR100_POSTOCC_ICG 13
+#define AONCRG_CLK_PUFRT_APB 14
+#define AONCRG_CLK_RTC_HMS_APB 15
+#define AONCRG_CLK_RTC_INTERNAL 16
+#define AONCRG_CLK_RTC_HMS_OSC32K 17
+#define AONCRG_CLK_RTC_HMS_CAL 18
+#define AONCRG_CLK_GMAC0_AXI128_AHB 19
+#define AONCRG_CLK_GMAC0_AXI128_MSTRCLK 20
+#define AONCRG_CLK_GMAC0_AXI128_AXI 21
+#define AONCRG_CLK_GMAC0_RMII_RTX 22
+#define AONCRG_CLK_GMAC0_AXI128_TX 23
+#define AONCRG_CLK_GMAC0_AXI128_TX_INV 24
+#define AONCRG_CLK_GMAC0_AXI128_RX 25
+#define AONCRG_CLK_GMAC0_AXI128_RX_INV 26
+#define AONCRG_CLK_GMAC0_GTXC 27
+#define AONCRG_CLK_XSPI_AXI 28
+#define AONCRG_CLK_XSPI_APB 29
+#define AONCRG_CLK_XSPI_XSPI_PHY 30
+#define AONCRG_CLK_TVSENSOR_PCLK 31
+#define AONCRG_CLK_TVSENSOR_TSADC 32
+#define AONCRG_CLK_TVSENSOR_BG 33
+#define AONCRG_CLK_MEU_PCLK_AP 34
+#define AONCRG_CLK_MEU_PCLK_SCP 35
+#define AONCRG_CLK_MEU_MEM_AXI 36
+#define AONCRG_CLK_AXIMEM_128B_ACLK 37
+#define AONCRG_CLK_APB2BISR_APB 38
+#define AONCRG_CLK_APB2BISR_BISR 39
+#define AONCRG_CLK_EMMC_S_PCLK 40
+#define AONCRG_CLK_EMMC_MSTRCLK 41
+#define AONCRG_CLK_EMMC 42
+#define AONCRG_CLK_EMMC_SDMCLK 43
+#define AONCRG_CLK_EMMC_SDPHY_PCLK 44
+#define AONCRG_CLK_SDIO0_PCLK 45
+#define AONCRG_CLK_SDIO0_MSTRCLK 46
+#define AONCRG_CLK_SDIO0 47
+#define AONCRG_CLK_SDIO0_SDMCLK 48
+#define AONCRG_CLK_SDIO0_SDPHY_PCLK 49
+#define AONCRG_CLK_HCLK 50
+#define AONCRG_CLK_ACLK 51
+#define AONCRG_CLK_PERF_MSTRCLK 52
+#define AONCRG_CLK_PERF_SLVCLK 53
+#define AONCRG_CLK_GCLK0 54
+#define AONCRG_CLK_GCLK_OSC 55
+#define AONCRG_CLK_RTC_ICG_EN 56
+#define AONCRG_CLK_GMAC0_ICG_EN 57
+#define AONCRG_CLK_XSPI_ICG_EN 58
+#define AONCRG_CLK_TVSENSOR0_ICG_EN 59
+#define AONCRG_CLK_MEU_ICG_EN 60
+#define AONCRG_CLK_APB2BISR_ICG_EN 61
+#define AONCRG_CLK_EMMC_ICG_EN 62
+#define AONCRG_CLK_SDIO0_ICG_EN 63
+#define AONCRG_CLK_TOP_ICG_EN 64
+
+#define AONCRG_CLK_END 65
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */
@@ -106,4 +106,22 @@
#define SYSCRG_SW_RSTN_DDR_TVSENSOR 3
#define SYSCRG_SW_RESET_NR_RESETS 4
+
+/*
+ * aoncrg
+ */
+#define AONCRG_RSTN_AON_IOMUX_PRESETN 0
+#define AONCRG_RSTN_RTC 1
+#define AONCRG_RSTN_GMAC0 2
+#define AONCRG_RSTN_XSPI 3
+#define AONCRG_RSTN_TVSENSOR 4
+#define AONCRG_RSTN_MEU 5
+#define AONCRG_RSTN_AXIMEM_128B_ARESET 6
+#define AONCRG_RSTN_APB2BISR_APB 7
+#define AONCRG_RSTN_SDIO0 8
+#define AONCRG_RSTN_EMMC 9
+#define AONCRG_RSTN_TOP 10
+#define AONCRG_RSTN_IRQ_CTRL 11
+
+#define AONCRG_RESET_NR_RESETS 12
#endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */