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Wed, 13 Dec 2023 14:47:54 -0800 (PST) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id bk21-20020a056830369500b006d855e2c56csm2375157otb.31.2023.12.13.14.47.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 14:47:54 -0800 (PST) From: Charlie Jenkins Date: Wed, 13 Dec 2023 14:47:48 -0800 Subject: [PATCH v3 2/2] documentation: Document PR_RISCV_SET_ICACHE_FLUSH_CTX prctl MIME-Version: 1.0 Message-Id: <20231213-fencei-v3-2-b75158238eb7@rivosinc.com> References: <20231213-fencei-v3-0-b75158238eb7@rivosinc.com> In-Reply-To: <20231213-fencei-v3-0-b75158238eb7@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet , Conor Dooley , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1702507670; l=4185; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=zPaRO2ks3l/75pkgWBpZ4nSSEIYV6K0VRBbOkUO2jEY=; b=FhysUS+fsKXjyq0qV4ESXY/r9f9YHqD57UdPggn5+823NiPGLggILNdzlx/BcMFogfJIEdvRy M8mdMMi6/hrBe52bmDrZrvSpfL+Om8qXAVgapW/bkUDvXMgqvt+LFBA X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231213_144755_695060_61DD2399 X-CRM114-Status: GOOD ( 18.58 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Provide documentation that explains how to properly do CMODX in riscv. Signed-off-by: Charlie Jenkins --- Documentation/arch/riscv/cmodx.rst | 98 ++++++++++++++++++++++++++++++++++++++ Documentation/arch/riscv/index.rst | 1 + 2 files changed, 99 insertions(+) diff --git a/Documentation/arch/riscv/cmodx.rst b/Documentation/arch/riscv/cmodx.rst new file mode 100644 index 000000000000..20f327d85116 --- /dev/null +++ b/Documentation/arch/riscv/cmodx.rst @@ -0,0 +1,98 @@ +.. SPDX-License-Identifier: GPL-2.0 + +============================================================================== +Concurrent Modification and Execution of Instructions (CMODX) for RISC-V Linux +============================================================================== + +CMODX is a programming technique where a program executes instructions that were +modified by the program itself. Instruction storage and the instruction cache +(icache) is not guaranteed to be synchronized on RISC-V hardware. Therefore, the +program must enforce its own synchonization with the unprivileged fence.i +instruction. + +However, the default Linux ABI prohibits the use of fence.i in userspace +applications. At any point the scheduler may migrate a task onto a new hart. If +migration occurs after the userspace synchronized the icache and instruction +storage with fence.i, the icache will no longer be clean. This is due to the +behavior of fence.i only affecting the hart that it is called on. Thus, the hart +that the task has been migrated to, may not have synchronized instruction +storage and icache. + +There are two ways to solve this problem: use the riscv_flush_icache() syscall, +or use the ``PR_RISCV_SET_ICACHE_FLUSH_CTX`` prctl(). The syscall should be used +when the application very rarely needs to flush the icache. If the icache will +need to be flushed many times in the lifetime of the application, the prctl +should be used. + +The prctl informs the kernel that it must emit synchronizing instructions upon +task migration. The program itself must emit synchonizing instructions when +necessary as well. + +1. prctl() Interface +--------------------- + +Before the program emits their first icache flushing instruction, the program +must call this prctl(). + +* prctl(PR_RISCV_SET_ICACHE_FLUSH_CTX, unsigned long ctx, unsigned long per_thread) + + Sets the icache flushing context. If per_thread is 0, context will be + applied per process, otherwise if per_thread is 1 context will be + per-thread. Any other number will have undefined behavior. + + * :c:macro:`PR_RISCV_CTX_SW_FENCEI`: Allow fence.i to be called in + userspace. + +Example usage: + +The following files are meant to be compiled and linked with each other. The +modify_instruction() function replaces an add with 0 with an add with one, +causing the instruction sequence in get_value() to change from returning a zero +to returning a one. + +cmodx.c:: + + #include + #include + + extern int get_value(); + extern void modify_instruction(); + + int main() + { + int value = get_value(); + printf("Value before cmodx: %d\n", value); + + // Call prctl before first fence.i is called inside modify_instruction + prctl(PR_RISCV_SET_ICACHE_FLUSH_CTX, PR_RISCV_CTX_SW_FENCEI, 0); + modify_instruction(); + + value = get_value(); + printf("Value after cmodx: %d\n", value); + return 0; + } + +cmodx.S:: + + .option norvc + + .text + .global modify_instruction + modify_instruction: + lw a0, new_insn + lui a5,%hi(old_insn) + sw a0,%lo(old_insn)(a5) + fence.i + ret + + .section modifiable, "awx" + .global get_value + get_value: + li a0, 0 + old_insn: + addi a0, a0, 0 + ret + + .data + new_insn: + addi a0, a0, 1 diff --git a/Documentation/arch/riscv/index.rst b/Documentation/arch/riscv/index.rst index 4dab0cb4b900..eecf347ce849 100644 --- a/Documentation/arch/riscv/index.rst +++ b/Documentation/arch/riscv/index.rst @@ -13,6 +13,7 @@ RISC-V architecture patch-acceptance uabi vector + cmodx features