| Message ID | 20231213113308.133176-4-cleger@rivosinc.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | riscv: hwprobe: add Zicond, Zam, Zacas and Ztso support | expand |
On Wed, Dec 13, 2023 at 12:32:59PM +0100, Clément Léger wrote: > Add description for the Zam ISA extension. > > Signed-off-by: Clément Léger <cleger@rivosinc.com> > --- > Documentation/devicetree/bindings/riscv/extensions.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > index 3574a0b70be4..912cc6a42eb4 100644 > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > @@ -171,6 +171,11 @@ properties: > memory types as ratified in the 20191213 version of the privileged > ISA specification. > > + - const: zam > + description: | > + The standard Zam extension for misaligned atomics is supported as > + ratified in version 20191213 of the riscv-isa-manual. Is "20191213" an actual tag in that repo? Looking at that version of the spec (because it is a spec version, but I don't think it is a valid reference to that repo) Zam is listed as Draft. In fact, in the most recent thing I could find, Zam was still listed as draft. Are you sure this is ratified?
On 14/12/2023 15:11, Conor Dooley wrote: > On Wed, Dec 13, 2023 at 12:32:59PM +0100, Clément Léger wrote: >> Add description for the Zam ISA extension. >> >> Signed-off-by: Clément Léger <cleger@rivosinc.com> >> --- >> Documentation/devicetree/bindings/riscv/extensions.yaml | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml >> index 3574a0b70be4..912cc6a42eb4 100644 >> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml >> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml >> @@ -171,6 +171,11 @@ properties: >> memory types as ratified in the 20191213 version of the privileged >> ISA specification. >> >> + - const: zam >> + description: | >> + The standard Zam extension for misaligned atomics is supported as >> + ratified in version 20191213 of the riscv-isa-manual. > > Is "20191213" an actual tag in that repo? Looking at that version of the > spec (because it is a spec version, but I don't think it is a valid > reference to that repo) Zam is listed as Draft. In fact, in the most > recent thing I could find, Zam was still listed as draft. Whoops, my bad, I assumed that the chapter being present in the spec meant it was ratified and I did not checked the listing stating it is still in draft. Will remove that from the next version. Thanks, Clément > > Are you sure this is ratified?
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 3574a0b70be4..912cc6a42eb4 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -171,6 +171,11 @@ properties: memory types as ratified in the 20191213 version of the privileged ISA specification. + - const: zam + description: | + The standard Zam extension for misaligned atomics is supported as + ratified in version 20191213 of the riscv-isa-manual. + - const: zba description: | The standard Zba bit-manipulation extension for address generation
Add description for the Zam ISA extension. Signed-off-by: Clément Léger <cleger@rivosinc.com> --- Documentation/devicetree/bindings/riscv/extensions.yaml | 5 +++++ 1 file changed, 5 insertions(+)