diff mbox series

[7/9] riscv: add ISA extension parsing for Zacas

Message ID 20231213113308.133176-8-cleger@rivosinc.com (mailing list archive)
State Changes Requested
Headers show
Series riscv: hwprobe: add Zicond, Zam, Zacas and Ztso support | expand

Checks

Context Check Description
conchuod/vmtest-for-next-PR warning PR summary
conchuod/patch-7-test-1 success .github/scripts/patches/build_rv32_defconfig.sh
conchuod/patch-7-test-2 success .github/scripts/patches/build_rv64_clang_allmodconfig.sh
conchuod/patch-7-test-3 success .github/scripts/patches/build_rv64_gcc_allmodconfig.sh
conchuod/patch-7-test-4 success .github/scripts/patches/build_rv64_nommu_k210_defconfig.sh
conchuod/patch-7-test-5 success .github/scripts/patches/build_rv64_nommu_virt_defconfig.sh
conchuod/patch-7-test-6 success .github/scripts/patches/checkpatch.sh
conchuod/patch-7-test-7 success .github/scripts/patches/dtb_warn_rv64.sh
conchuod/patch-7-test-8 success .github/scripts/patches/header_inline.sh
conchuod/patch-7-test-9 success .github/scripts/patches/kdoc.sh
conchuod/patch-7-test-10 success .github/scripts/patches/module_param.sh
conchuod/patch-7-test-11 success .github/scripts/patches/verify_fixes.sh
conchuod/patch-7-test-12 success .github/scripts/patches/verify_signedoff.sh

Commit Message

Clément Léger Dec. 13, 2023, 11:33 a.m. UTC
Add parsing for Zacas ISA extension which was ratified recently in the
riscv-zacas manual.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 arch/riscv/include/asm/hwcap.h | 1 +
 arch/riscv/kernel/cpufeature.c | 1 +
 2 files changed, 2 insertions(+)
diff mbox series

Patch

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 016faa08c8ba..8aee032f092f 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -86,6 +86,7 @@ 
 #define RISCV_ISA_EXT_ZFA		71
 #define RISCV_ISA_EXT_ZTSO		72
 #define RISCV_ISA_EXT_ZAM		73
+#define RISCV_ISA_EXT_ZACAS		74
 
 #define RISCV_ISA_EXT_MAX		128
 #define RISCV_ISA_EXT_INVALID		U32_MAX
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index e999320398b7..62443cd632b8 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -259,6 +259,7 @@  const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL),
 	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
 	__RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
+	__RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
 	__RISCV_ISA_EXT_DATA(zam, RISCV_ISA_EXT_ZAM),
 	__RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA),
 	__RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),