From patchwork Mon Dec 25 10:33:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 13504585 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 59E1FC3DA6E for ; Mon, 25 Dec 2023 10:35:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Cc:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=cFHoes/bD6qwCWdoekVkTjreXzT7phJOFVJqymQfWMk=; b=A9Zab6Z90oL3fF YHYVOYwIruLwST6/RoHNoeetdueOcCfuprQtBmmVRAUoD44Vs96p/NrQXyd6gntjNiRry6MlXTLYk fpdWwQPej3b/M67xWfKOulX7Sn7b+lGyV1pRWO4wBArvBKStpxmo2Bdr6KZClqqbRcRTtXBI7tP80 aPebceIftZJ7DS06zF3aI53Wii3TLeBkY3E5JAXdktadaL20iQLHX89VoT8s6rQv/MJABPhULTFrd gew0z+yC342oR9q7EACfLiq22ZMmBkS+Z/5phlxoSas5wiDZH4nw0XQ/OgboQdGO2e7LfvCMXTiqZ rkZoRtl8IXCYYsQFwVgA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rHiJ7-00AYUQ-1x; Mon, 25 Dec 2023 10:35:37 +0000 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rHiIY-00AY8g-2F; Mon, 25 Dec 2023 10:35:06 +0000 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BPAYDlm093342; Mon, 25 Dec 2023 18:34:13 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Mon, 25 Dec 2023 18:34:10 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v6 12/16] riscv: dts: sophgo: Add T-Head PMU extension for cv1800b Date: Mon, 25 Dec 2023 18:33:04 +0800 Message-ID: <20231225103308.1557548-13-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231225103308.1557548-1-peterlin@andestech.com> References: <20231225103308.1557548-1-peterlin@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3BPAYDlm093342 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231225_023503_262645_7B78C174 X-CRM114-Status: UNSURE ( 8.05 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org xtheadpmu stands for T-Head Performance Monitor Unit extension. Based on the added T-Head PMU ISA string, the SBI PMU driver will make use of the non-standard irq source. Signed-off-by: Yu Chien Peter Lin Acked-by: Conor Dooley --- Changes v4 -> v5: - New patch Changes v5 -> v6: - Include Conor's Acked-by --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi index aec6401a467b..8c0143f0a01b 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -29,7 +29,7 @@ cpu0: cpu@0 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadpmu"; cpu0_intc: interrupt-controller { compatible = "riscv,cpu-intc";