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Mon, 8 Jan 2024 11:07:01 +0000 Received: from SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn ([fe80::e6aa:baea:fd8c:4cd2]) by SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn ([fe80::e6aa:baea:fd8c:4cd2%7]) with mapi id 15.20.7135.032; Mon, 8 Jan 2024 11:07:01 +0000 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , Daire McNamara , Emil Renner Berthing , Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-pci@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v14 20/22] PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value Date: Mon, 8 Jan 2024 19:06:10 +0800 Message-Id: <20240108110612.19048-21-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240108110612.19048-1-minda.chen@starfivetech.com> References: <20240108110612.19048-1-minda.chen@starfivetech.com> X-ClientProxiedBy: ZQ0PR01CA0014.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:5::19) To SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:25::15) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SHXPR01MB0863:EE_|SHXPR01MB0797:EE_ X-MS-Office365-Filtering-Correlation-Id: c41f4676-138d-417d-e107-08dc1039f0a7 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; 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As described in PCI base specification r6.0, section 6.6.1 , there are two different use cases of the value: - "With a Downstream Port that does not support Link speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms following exit from a Conventional Reset before sending a Configuration Request to the device immediately below that Port." - "With a Downstream Port that supports Link speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms after Link training completes before sending a Configuration Request to the device immediately below that Port." Signed-off-by: Kevin Xie Reviewed-by: Mason Huo Acked-by: Bjorn Helgaas --- drivers/pci/pci.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index f43873049d52..6990146e14e3 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -22,6 +22,22 @@ */ #define PCIE_PME_TO_L2_TIMEOUT_US 10000 +/* + * As described in PCI base specification r6.0, section 6.6.1 , there are two different use cases of the value: + * + * - "With a Downstream Port that does not support Link speeds greater + * than 5.0 GT/s, software must wait a minimum of 100 ms following exit + * from a Conventional Reset before sending a Configuration Request to + * the device immediately below that Port." + * + * - "With a Downstream Port that supports Link speeds greater than + * 5.0 GT/s, software must wait a minimum of 100 ms after Link training + * completes before sending a Configuration Request to the device + * immediately below that Port." + */ +#define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100 + extern const unsigned char pcie_link_speed[]; extern bool pci_early_dump;