From patchwork Wed Jan 10 07:39:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-Chien Peter Lin X-Patchwork-Id: 13515722 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 10F0AC3DA6E for ; Wed, 10 Jan 2024 07:41:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Cc:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=uszWqNAgiliYJcVVK6/Tzs3WRnWQI5yA/gUqFfmSAxo=; b=Z43BigdfUU0MPw LdxHIgZF2qXYYiMQHa9zDQ7zE5Fv7MKhFOKxRGx4XEyLez9cuiIvYHsp2RSARXQOQdS6em8+iEQMp Q23rA6jNKp88pb9Qv0SR3cfAkvIqxpoLU6uyba/OhvmhVNv+IOZVSL3XA62BrV4CX1zzCG0p8baIU WYCrK+nw+wD2Svhmb0XhcDslSwV58Y3ig3v6D4JManJd2TzzCv0Dv+kIwRWAJi/W2MKM9HRRCKK5a vyN4eGBvYwcYh7XuBioEEojnIIkZxkO2MhMOKqpVuMfp8duDUqk0UCpoGlTRD/ePVjhlHuKIN7yNj vaMuPdIBjhAGlQSxaXCQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rNTDi-00Adj5-2p; Wed, 10 Jan 2024 07:41:50 +0000 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rNTDJ-00AdPI-18; Wed, 10 Jan 2024 07:41:27 +0000 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 40A7ecKY086847; Wed, 10 Jan 2024 15:40:38 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 10 Jan 2024 15:40:33 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 14/16] riscv: dts: thead: Add T-Head PMU extension for th1520 Date: Wed, 10 Jan 2024 15:39:15 +0800 Message-ID: <20240110073917.2398826-15-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240110073917.2398826-1-peterlin@andestech.com> References: <20240110073917.2398826-1-peterlin@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 40A7ecKY086847 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240109_234125_837042_6380774C X-CRM114-Status: UNSURE ( 8.18 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org xtheadpmu stands for T-Head Performance Monitor Unit extension. Based on the added T-Head PMU ISA string, the SBI PMU driver will make use of the non-standard irq source. Signed-off-by: Yu Chien Peter Lin Acked-by: Conor Dooley --- Changes v4 -> v5: - New patch Changes v5 -> v6: - Include Conor's Acked-by Changes v6 -> v7: - No change --- arch/riscv/boot/dts/thead/th1520.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index ba4d2c673ac8..2dad2b22824a 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -22,7 +22,7 @@ c910_0: cpu@0 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadpmu"; reg = <0>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -46,7 +46,7 @@ c910_1: cpu@1 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadpmu"; reg = <1>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -70,7 +70,7 @@ c910_2: cpu@2 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadpmu"; reg = <2>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -94,7 +94,7 @@ c910_3: cpu@3 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadpmu"; reg = <3>; i-cache-block-size = <64>; i-cache-size = <65536>;