From patchwork Thu Jan 25 14:59:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13531073 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 21CA0C48260 for ; Thu, 25 Jan 2024 15:12:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=/JujQmmYKMrL1dp6ATAt/m9nflAb7CdkzRQixC7SAH4=; b=4/NkoFi7AolqmZ RwUxRfjZjDCRC+pR4klExdHMMV5e4MZb/oTU02fZFym4PGiC9rYholVMWT532w8wDE4z7jMYvASEf dOjjdlLy6Kx0pLfUM8eTOlTMStLIMNmwY20JFyN5u6b1NgJapX5QisyhOB6u+lOqopoLyP/2m0GvM IlLFLLY4zFMelaYGzw9HZgfMGuLKiyJuvH7DtmgvHiju9YmmORhgTL776/rJCFQHSDl/c4jGaKmXT 7bbOT/j8wcuz/BK7mklC4P7Fr4wTv4AQxCKimvfubJ7X1UmtdXZi/9JkOwOwNUktHqK29qL9z0nUA qYrl0x/hkMfbFDtwKzDA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rT1Oe-00000000Yfa-1vK7; Thu, 25 Jan 2024 15:12:04 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rT1Ob-00000000Ydh-125a for linux-riscv@lists.infradead.org; Thu, 25 Jan 2024 15:12:02 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id B402161EE6; Thu, 25 Jan 2024 15:12:00 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 08165C433C7; Thu, 25 Jan 2024 15:11:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1706195520; bh=lQa90hyBkLuNQGPI6gmRovggw7RSn4HqbLkZoyCISio=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DSvxk841kVJVmEf4He8NwMxVcYFLyFxsuI674Ebdd4b6L1RX4gAcaCYBnXUxFlaP7 p0a7XMaGgLwMu9eLSvy2e4HRngLmNotdK6jT+id/Ta+sSK5JumdHcVKChRiqAOTt7W i45ayymlz9m5T36KREF7ZYyUxFYddYN8TuQXbVVhaEJYUGz5x0fuPv/L8ChhkvbNRV gkI48DkJdAPmLS6vbaGRAx7xZRmzIzGt0AahTuW2S7d94uawJQm7xE5j0MJEHxhZt/ 7UBJc/rrtAChZ916eK0pwGYfJv2j3KVEpscpLDQy1kWrRBdzJ7lCT+WnTt5esCkQME Jr9iJ+lMf1/4A== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Andrea Parri Subject: [PATCH v3 2/2] riscv: cmpxchg: implement arch_cmpxchg64_{relaxed|acquire|release} Date: Thu, 25 Jan 2024 22:59:07 +0800 Message-ID: <20240125145908.968-3-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240125145908.968-1-jszhang@kernel.org> References: <20240125145908.968-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240125_071201_389759_50094FB5 X-CRM114-Status: UNSURE ( 9.84 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org After selecting ARCH_USE_CMPXCHG_LOCKREF, one straight futher optimization is implementing the arch_cmpxchg64_relaxed() because the lockref code does not need the cmpxchg to have barrier semantics. At the same time, implement arch_cmpxchg64_acquire and arch_cmpxchg64_release as well. However, on both TH1520 and JH7110 platforms, I didn't see obvious performance improvement with Linus' test case [1]. IMHO, this may be related with the fence and lr.d/sc.d hw implementations. In theory, lr/sc without fence could give performance improvement over lr/sc plus fence, so add the code here to leave performance improvement room on newer HW platforms. Link: http://marc.info/?l=linux-fsdevel&m=137782380714721&w=4 [1] Signed-off-by: Jisheng Zhang Reviewed-by: Andrea Parri --- arch/riscv/include/asm/cmpxchg.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index 2f4726d3cfcc..6318187f426f 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -360,4 +360,22 @@ arch_cmpxchg_relaxed((ptr), (o), (n)); \ }) +#define arch_cmpxchg64_relaxed(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ + arch_cmpxchg_relaxed((ptr), (o), (n)); \ +}) + +#define arch_cmpxchg64_acquire(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ + arch_cmpxchg_acquire((ptr), (o), (n)); \ +}) + +#define arch_cmpxchg64_release(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ + arch_cmpxchg_release((ptr), (o), (n)); \ +}) + #endif /* _ASM_RISCV_CMPXCHG_H */