Message ID | 20240222083946.3977135-10-peterlin@andestech.com (mailing list archive) |
---|---|
State | Accepted |
Commit | 270fc77e7b0e38964635c2c5d87ad354dbd2cd34 |
Headers | show |
Series | Support Andes PMU extension | expand |
On Thu, Feb 22, 2024 at 9:41 AM Yu Chien Peter Lin <peterlin@andestech.com> wrote: > xandespmu stands for Andes Performance Monitor Unit extension. > Based on the added Andes PMU ISA string, the SBI PMU driver > will make use of the non-standard irq source. > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Acked-by: Conor Dooley <conor.dooley@microchip.com> > --- > Changes v1 -> v2: > - New patch > Changes v2 -> v3: > - No change > Changes v3 -> v4: > - No change > Changes v4 -> v5: > - Include Geert's Reviewed-by > - Include Prabhakar's Reviewed/Tested-by > Changes v5 -> v6: > - Include Conor's Acked-by > Changes v6 -> v7: > - No change > Changes v7 -> v8: > - No change > Changes v8 -> v9: > - No change Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> so Palmer can pick it up with the rest of the series (the Renesas tree merge window for v6.9 has closed) Gr{oetje,eeting}s, Geert
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index 099f3df75b42..d7a66043f13b 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -27,7 +27,7 @@ cpu0: cpu@0 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xandespmu"; mmu-type = "riscv,sv39"; i-cache-size = <0x8000>; i-cache-line-size = <0x40>;