| Message ID | 20240222083946.3977135-6-peterlin@andestech.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 95113bb705157f3518cec4ff0225a922507a0f8b |
| Headers | show |
| Series | Support Andes PMU extension | expand |
On Thu, Feb 22, 2024 at 9:40 AM Yu Chien Peter Lin <peterlin@andestech.com> wrote: > The Andes hart-level interrupt controller (Andes INTC) allows AX45MP > cores to handle custom local interrupts, such as the performance > counter overflow interrupt. > > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > Changes v1 -> v2: > - New patch > Changes v2 -> v3: > - Fixed possible compatibles for Andes INTC > Changes v3 -> v4: > - No change > Changes v4 -> v5: > - Include Geert's Reviewed-by > - Include Prabhakar's Reviewed/Tested-by > Changes v5 -> v6: > - No change > Changes v6 -> v7: > - No change > Changes v7 -> v8: > - No change > Changes v8 -> v9: > - No change Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> so Palmer can pick it up with the rest of the series (the Renesas tree imerge window for v6.9 has closed) Gr{oetje,eeting}s, Geert
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index a92cfcfc021b..099f3df75b42 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -39,7 +39,7 @@ cpu0: cpu@0 { cpu0_intc: interrupt-controller { #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; + compatible = "andestech,cpu-intc", "riscv,cpu-intc"; interrupt-controller; }; };