From patchwork Thu Feb 29 01:01:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 13576377 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8B4E2C5475B for ; Thu, 29 Feb 2024 01:03:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=0zog58Zkkr6RQGT2/Ux1rivEj/9uCi+ghlu4aCP93K8=; b=0Lu+/NtR8Ufxvf NgR2mIdDyqWE+gKxPL53aZC1RA+43kEO0PaUcwvCuTkNR/WDnkNb7lMa9q0cdcNQlUcKVZvfRpfYl 2bREyb+dXXqvvGiKcLruJNKfyb8XwjuR3UW3wAf6rMYuGIVQsspogMB48OB9gwG0neI2g/eCENuo8 2uniEhyiTLEdVRNMYFl0Q5MJf/VyGHP1zLoMYc9OSHmxmdFzjj778CotQ4+bwkGIwXQPC3ZiLb+lX fsDlqZKSiOLJNXYxd3oA+b2FiD+DVXxqXyH9B52ertyOcSwbqoiHZnTltPXYcbKr2Q2eliTdOq3CT N4fu2f/cCTkt9WzW5uQA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rfUpT-0000000BXAO-2fT8; Thu, 29 Feb 2024 01:03:19 +0000 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rfUoI-0000000BWGy-26rJ for linux-riscv@lists.infradead.org; Thu, 29 Feb 2024 01:02:14 +0000 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1dc09556599so3811165ad.1 for ; Wed, 28 Feb 2024 17:02:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1709168525; x=1709773325; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2qc8/YsnWZLtzQVcnf6euk9w8bwSYLeSpKUiQ52ang8=; b=Ic0ZNT8goe2wBnPJIEG+DZ8Jlb9Y+ZesRAA8rqvge8+LhNWTs0rtxJwOc7qlthb7Bz 4h/VagWLM95rf6aYpt9MoLgohff2kTPRFe0mJNxJap7d4/k3Rha6SuILszLnjJ2nHgLc d/cVlmJMeStus1OEZAIiGmTXj9GcXwbOfdBLn3AM8BJnr8DZq/4kViaRGVVF5Q3CgcHh 0s9IeE8/gNr58KJUTQVRBO4hlM3z8rRGcI6Pg/v5FppdtpmbX4HLHJVK/78B33WQEaO9 v1quMF7PY/4ERt/ZLnn6aupLwRnIt3ZBMAK+lLuh3wFSCLJXp0zcOqO/AyNlb8IOfoHx 4d1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709168525; x=1709773325; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2qc8/YsnWZLtzQVcnf6euk9w8bwSYLeSpKUiQ52ang8=; b=YqCEiCbBjATlkr4a77AtNerUnKi1QPqR/TCVvyItnq2ffPHW3X6oYwvLDvDzCqaebW VAkT8tIXkZCxxtIzk8JLxRERi9rPWePTlmLC1oSwn94U/C68FmvgYxENToCWHVTzEubi kK+5QIU4gwSWonE1xECorV5ELwexuYMezdxjaTkJeDiw4MiMAWY8EZAINdZOnAUVQWuE emQWMUIHAKecXV2WyH0DmJBhAX7pll8VP33Hz8Xjd4Xd1OWUdwbCa52nFh9CjmUO2oVU YaLgmVwLMu8VGUxKDhNb1KvwoBLygzEDlLBDpH4xMOjaNNy3Cb6pguDCQtjVD5jtJNnh YEsw== X-Forwarded-Encrypted: i=1; AJvYcCV+cRZSXqFT9CbcQby8+aVMBI0muGjP5ZNOtf/IX9poUhI+9CeXq2RU5E8S8Bk/lcetWweCMaDXPBCD+21S8Zifsw7dMYCh9YXwobGYlfex X-Gm-Message-State: AOJu0YwjCR5iCOim6gQ0bJciIgzB5bAu5nYCoGhDFBVdwanU/A1AwKAm ztgHDus2DCJtFbCd3jS46r15y32+gkewvldaB3vU+N/smuahBMnQom3nfUVD8kA= X-Google-Smtp-Source: AGHT+IE+6zkbqEfxrFsGgHeVaj3fDKJqNlgYGDvcDCj1su/jbaCelp928OgUnJ+avO8FLYt/A5miDA== X-Received: by 2002:a17:902:d2d1:b0:1db:f033:9f9b with SMTP id n17-20020a170902d2d100b001dbf0339f9bmr793352plc.9.1709168523952; Wed, 28 Feb 2024 17:02:03 -0800 (PST) Received: from atishp.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id j14-20020a170902da8e00b001dc8d6a9d40sm78043plx.144.2024.02.28.17.02.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Feb 2024 17:02:03 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Subject: [PATCH v4 13/15] KVM: riscv: selftests: Add SBI PMU selftest Date: Wed, 28 Feb 2024 17:01:28 -0800 Message-Id: <20240229010130.1380926-14-atishp@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240229010130.1380926-1-atishp@rivosinc.com> References: <20240229010130.1380926-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240228_170206_737063_D5675E74 X-CRM114-Status: GOOD ( 22.00 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , linux-kselftest@vger.kernel.org, Albert Ou , Alexandre Ghiti , kvm@vger.kernel.org, Will Deacon , Anup Patel , Paul Walmsley , Atish Patra , Conor Dooley , Paolo Bonzini , Guo Ren , kvm-riscv@lists.infradead.org, Atish Patra , Palmer Dabbelt , linux-riscv@lists.infradead.org, Shuah Khan , Andrew Jones Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This test implements basic sanity test and cycle/instret event counting tests. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- tools/testing/selftests/kvm/Makefile | 1 + tools/testing/selftests/kvm/riscv/sbi_pmu.c | 340 ++++++++++++++++++++ 2 files changed, 341 insertions(+) create mode 100644 tools/testing/selftests/kvm/riscv/sbi_pmu.c diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile index 426f85798aea..b2dce6843b9e 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -195,6 +195,7 @@ TEST_GEN_PROGS_riscv += kvm_create_max_vcpus TEST_GEN_PROGS_riscv += kvm_page_table_test TEST_GEN_PROGS_riscv += set_memory_region_test TEST_GEN_PROGS_riscv += steal_time +TEST_GEN_PROGS_riscv += riscv/sbi_pmu SPLIT_TESTS += arch_timer SPLIT_TESTS += get-reg-list diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu.c b/tools/testing/selftests/kvm/riscv/sbi_pmu.c new file mode 100644 index 000000000000..fc1fc5eea99e --- /dev/null +++ b/tools/testing/selftests/kvm/riscv/sbi_pmu.c @@ -0,0 +1,340 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * arch_timer.c - Tests the riscv64 sstc timer IRQ functionality + * + * The test validates the sstc timer IRQs using vstimecmp registers. + * It's ported from the aarch64 arch_timer test. + * + * Copyright (c) 2024, Rivos Inc. + */ + +#include +#include +#include +#include +#include +#include "kvm_util.h" +#include "test_util.h" +#include "processor.h" + +/* Maximum counters (firmware + hardware)*/ +#define RISCV_MAX_PMU_COUNTERS 64 +union sbi_pmu_ctr_info ctrinfo_arr[RISCV_MAX_PMU_COUNTERS]; + +/* Cache the available counters in a bitmask */ +static unsigned long counter_mask_available; + +unsigned long pmu_csr_read_num(int csr_num) +{ +#define switchcase_csr_read(__csr_num, __val) {\ + case __csr_num: \ + __val = csr_read(__csr_num); \ + break; } +#define switchcase_csr_read_2(__csr_num, __val) {\ + switchcase_csr_read(__csr_num + 0, __val) \ + switchcase_csr_read(__csr_num + 1, __val)} +#define switchcase_csr_read_4(__csr_num, __val) {\ + switchcase_csr_read_2(__csr_num + 0, __val) \ + switchcase_csr_read_2(__csr_num + 2, __val)} +#define switchcase_csr_read_8(__csr_num, __val) {\ + switchcase_csr_read_4(__csr_num + 0, __val) \ + switchcase_csr_read_4(__csr_num + 4, __val)} +#define switchcase_csr_read_16(__csr_num, __val) {\ + switchcase_csr_read_8(__csr_num + 0, __val) \ + switchcase_csr_read_8(__csr_num + 8, __val)} +#define switchcase_csr_read_32(__csr_num, __val) {\ + switchcase_csr_read_16(__csr_num + 0, __val) \ + switchcase_csr_read_16(__csr_num + 16, __val)} + + unsigned long ret = 0; + + switch (csr_num) { + switchcase_csr_read_32(CSR_CYCLE, ret) + switchcase_csr_read_32(CSR_CYCLEH, ret) + default : + break; + } + + return ret; +#undef switchcase_csr_read_32 +#undef switchcase_csr_read_16 +#undef switchcase_csr_read_8 +#undef switchcase_csr_read_4 +#undef switchcase_csr_read_2 +#undef switchcase_csr_read +} + +static inline void dummy_func_loop(int iter) +{ + int i = 0; + + while (i < iter) { + asm volatile("nop"); + i++; + } +} + +static void guest_illegal_exception_handler(struct ex_regs *regs) +{ + __GUEST_ASSERT(regs->cause == EXC_INST_ILLEGAL, + "Unexpected exception handler %lx\n", regs->cause); + + /* skip the trapping instruction */ + regs->epc += 4; +} + +static unsigned long get_counter_index(unsigned long cbase, unsigned long cmask, + unsigned long cflags, + unsigned long event) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, cmask, + cflags, event, 0, 0); + __GUEST_ASSERT(ret.error == 0, "config matching failed %ld\n", ret.error); + GUEST_ASSERT((ret.value < RISCV_MAX_PMU_COUNTERS) && + ((1UL << ret.value) & counter_mask_available)); + + return ret.value; +} + +static unsigned long get_num_counters(void) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_NUM_COUNTERS, 0, 0, 0, 0, 0, 0); + + __GUEST_ASSERT(ret.error == 0, "Unable to retrieve number of counters from SBI PMU"); + + __GUEST_ASSERT(ret.value < RISCV_MAX_PMU_COUNTERS, + "Invalid number of counters %ld\n", ret.value); + + return ret.value; +} + +static void update_counter_info(int num_counters) +{ + int i = 0; + struct sbiret ret; + + for (i = 0; i < num_counters; i++) { + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_GET_INFO, i, 0, 0, 0, 0, 0); + + /* There can be gaps in logical counter indicies*/ + if (!ret.error) + GUEST_ASSERT_NE(ret.value, 0); + + ctrinfo_arr[i].value = ret.value; + counter_mask_available |= BIT(i); + } + + GUEST_ASSERT(counter_mask_available > 0); +} + +static unsigned long read_counter(int idx, union sbi_pmu_ctr_info ctrinfo) +{ + unsigned long counter_val = 0; + struct sbiret ret; + + __GUEST_ASSERT(ctrinfo.type < 2, "Invalid counter type %d", ctrinfo.type); + + if (ctrinfo.type == SBI_PMU_CTR_TYPE_HW) { + counter_val = pmu_csr_read_num(ctrinfo.csr); + } else if (ctrinfo.type == SBI_PMU_CTR_TYPE_FW) { + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ, idx, 0, 0, 0, 0, 0); + GUEST_ASSERT(ret.error == 0); + counter_val = ret.value; + } + + return counter_val; +} + +static void start_counter(unsigned long counter, unsigned long start_flags, + unsigned long ival) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, counter, 1, start_flags, + ival, 0, 0); + __GUEST_ASSERT(ret.error == 0, "Unable to start counter %ld\n", counter); +} + +static void stop_counter(unsigned long counter, unsigned long stop_flags) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, counter, 1, stop_flags, + 0, 0, 0); + if (stop_flags & SBI_PMU_STOP_FLAG_RESET) + __GUEST_ASSERT(ret.error == SBI_ERR_ALREADY_STOPPED, + "Unable to stop counter %ld\n", counter); + else + __GUEST_ASSERT(ret.error == 0, "Unable to stop counter %ld error %ld\n", + counter, ret.error); +} + +static void test_pmu_event(unsigned long event) +{ + unsigned long counter; + unsigned long counter_value_pre, counter_value_post; + unsigned long counter_init_value = 100; + + counter = get_counter_index(0, counter_mask_available, 0, event); + counter_value_pre = read_counter(counter, ctrinfo_arr[counter]); + + /* Do not set the initial value */ + start_counter(counter, 0, counter_init_value); + dummy_func_loop(10000); + + stop_counter(counter, 0); + + counter_value_post = read_counter(counter, ctrinfo_arr[counter]); + __GUEST_ASSERT(counter_value_post > counter_value_pre, + "counter_value_post %lx counter_value_pre %lx\n", + counter_value_post, counter_value_pre); + + /* Now set the initial value and compare */ + start_counter(counter, SBI_PMU_START_FLAG_SET_INIT_VALUE, counter_init_value); + dummy_func_loop(10000); + + stop_counter(counter, 0); + + counter_value_post = read_counter(counter, ctrinfo_arr[counter]); + __GUEST_ASSERT(counter_value_post > counter_init_value, + "counter_value_post %lx counter_init_value %lx\n", + counter_value_post, counter_init_value); + + stop_counter(counter, SBI_PMU_STOP_FLAG_RESET); +} + +static void test_invalid_event(void) +{ + struct sbiret ret; + unsigned long event = 0x1234; /* A random event */ + + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, 0, + counter_mask_available, 0, event, 0, 0); + GUEST_ASSERT_EQ(ret.error, SBI_ERR_NOT_SUPPORTED); +} + +static void test_pmu_events(int cpu) +{ + int num_counters = 0; + + /* Get the counter details */ + num_counters = get_num_counters(); + update_counter_info(num_counters); + + /* Sanity testing for any random invalid event */ + test_invalid_event(); + + /* Only these two events are guranteed to be present */ + test_pmu_event(SBI_PMU_HW_CPU_CYCLES); + test_pmu_event(SBI_PMU_HW_INSTRUCTIONS); + + GUEST_DONE(); +} + +static void test_pmu_basic_sanity(int cpu) +{ + long out_val = 0; + bool probe; + struct sbiret ret; + int num_counters = 0, i; + unsigned long counter_val = -1; + union sbi_pmu_ctr_info ctrinfo; + + probe = guest_sbi_probe_extension(SBI_EXT_PMU, &out_val); + GUEST_ASSERT(probe && out_val == 1); + + num_counters = get_num_counters(); + + for (i = 0; i < num_counters; i++) { + ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_GET_INFO, i, + 0, 0, 0, 0, 0); + + /* There can be gaps in logical counter indicies*/ + if (!ret.error) + GUEST_ASSERT_NE(ret.value, 0); + else + continue; + + ctrinfo.value = ret.value; + + /* Accesibility check of hardware and read capability of firmware counters */ + counter_val = read_counter(i, ctrinfo); + /* The spec doesn't mandate any initial value. Verify if a sane value */ + GUEST_ASSERT_NE(counter_val, -1); + } + + GUEST_DONE(); +} + +static void run_vcpu(struct kvm_vcpu *vcpu) +{ + struct ucall uc; + + vcpu_run(vcpu); + switch (get_ucall(vcpu, &uc)) { + case UCALL_ABORT: + REPORT_GUEST_ASSERT(uc); + break; + case UCALL_DONE: + case UCALL_SYNC: + break; + default: + TEST_FAIL("Unknown ucall %lu", uc.cmd); + break; + } +} + +void test_vm_destroy(struct kvm_vm *vm) +{ + memset(ctrinfo_arr, 0, sizeof(union sbi_pmu_ctr_info) * RISCV_MAX_PMU_COUNTERS); + counter_mask_available = 0; + kvm_vm_free(vm); +} + +static void test_vm_basic_test(void *guest_code) +{ + struct kvm_vm *vm; + struct kvm_vcpu *vcpu; + + vm = vm_create_with_one_vcpu(&vcpu, guest_code); + __TEST_REQUIRE(__vcpu_has_ext(vcpu, RISCV_ISA_EXT_REG(KVM_RISCV_SBI_EXT_PMU)), + "SBI PMU not available, skipping test"); + vm_init_vector_tables(vm); + /* Illegal instruction handler is required to verify read access without configuration */ + vm_install_exception_handler(vm, EXC_INST_ILLEGAL, guest_illegal_exception_handler); + + vcpu_init_vector_tables(vcpu); + vcpu_args_set(vcpu, 1, 0); + run_vcpu(vcpu); + + test_vm_destroy(vm); +} + +static void test_vm_events_test(void *guest_code) +{ + struct kvm_vm *vm = NULL; + struct kvm_vcpu *vcpu = NULL; + + vm = vm_create_with_one_vcpu(&vcpu, guest_code); + __TEST_REQUIRE(__vcpu_has_ext(vcpu, RISCV_ISA_EXT_REG(KVM_RISCV_SBI_EXT_PMU)), + "SBI PMU not available, skipping test"); + vcpu_args_set(vcpu, 1, 0); + run_vcpu(vcpu); + + test_vm_destroy(vm); +} + +int main(void) +{ + test_vm_basic_test(test_pmu_basic_sanity); + pr_info("SBI PMU basic test : PASS\n"); + + test_vm_events_test(test_pmu_events); + pr_info("SBI PMU event verification test : PASS\n"); + + return 0; +}