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Signed-off-by: Joshua Yeong --- arch/riscv/Kconfig.errata | 21 ++++++ arch/riscv/errata/Makefile | 1 + arch/riscv/errata/starfive/Makefile | 1 + arch/riscv/errata/starfive/errata.c | 95 ++++++++++++++++++++++++++++ arch/riscv/include/asm/alternative.h | 3 + arch/riscv/include/asm/errata_list.h | 5 ++ arch/riscv/kernel/alternative.c | 5 ++ 7 files changed, 131 insertions(+) create mode 100644 arch/riscv/errata/starfive/Makefile create mode 100644 arch/riscv/errata/starfive/errata.c diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index 910ba8837add..1438dd09533b 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -53,6 +53,16 @@ config ERRATA_SIFIVE_CIP_1200 If you don't know what to do here, say "Y". +config ERRATA_STARFIVE + bool "StarFive errata" + depends on RISCV_ALTERNATIVE + help + All StarFive errata Kconfig depend on this Kconfig. Disabling + this Kconfig will disable all StarFive errata. Please say "Y" + here if your platform uses StarFive CPU cores. + + Otherwise, please say "N" here to avoid unnecessary overhead. + config ERRATA_STARFIVE_JH7100 bool "StarFive JH7100 support" depends on ARCH_STARFIVE @@ -72,6 +82,17 @@ config ERRATA_STARFIVE_JH7100 Say "Y" if you want to support the BeagleV Starlight and/or StarFive VisionFive V1 boards. +config ERRATA_STARFIVE_CMO + bool "Apply StarFive cache management errata" + depends on ERRATA_STARFIVE && MMU + select RISCV_DMA_NONCOHERENT + default y + help + This will apply the cache management errata to handle the + non-standard handling on non-coherent operations on StarFive cores. + + If you don't know what to do here, say "Y". + config ERRATA_THEAD bool "T-HEAD errata" depends on RISCV_ALTERNATIVE diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile index 8a2739485123..4713a686b9f7 100644 --- a/arch/riscv/errata/Makefile +++ b/arch/riscv/errata/Makefile @@ -4,4 +4,5 @@ endif obj-$(CONFIG_ERRATA_ANDES) += andes/ obj-$(CONFIG_ERRATA_SIFIVE) += sifive/ +obj-$(CONFIG_ERRATA_STARFIVE) += starfive/ obj-$(CONFIG_ERRATA_THEAD) += thead/ diff --git a/arch/riscv/errata/starfive/Makefile b/arch/riscv/errata/starfive/Makefile new file mode 100644 index 000000000000..2d644e19caef --- /dev/null +++ b/arch/riscv/errata/starfive/Makefile @@ -0,0 +1 @@ +obj-y += errata.o diff --git a/arch/riscv/errata/starfive/errata.c b/arch/riscv/errata/starfive/errata.c new file mode 100644 index 000000000000..3ee360cd5e81 --- /dev/null +++ b/arch/riscv/errata/starfive/errata.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Erratas to be applied for StarFive CPU cores + * + * Copyright (C) 2024 Shanghai StarFive Technology Co., Ltd. + * + * Author: Joshua Yeong + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define STARFIVE_JH8100_DUBHE90_MARCHID 0x80000000DB000090UL +#define STARFIVE_JH8100_DUBHE90_MIMPID 0x0000000020230930UL +#define STARFIVE_JH8100_DUBHE80_MARCHID 0x80000000DB000080UL +#define STARFIVE_JH8100_DUBHE80_MIMPID 0x0000000020230831UL +#define STARFIVE_JH8100_L3 0x40 + +static bool errata_probe_cmo(unsigned int stage, unsigned long arch_id, + unsigned long impid) +{ + if (!IS_ENABLED(CONFIG_ERRATA_STARFIVE_CMO)) + return false; + + if ((arch_id != STARFIVE_JH8100_DUBHE90_MARCHID || + impid != STARFIVE_JH8100_DUBHE90_MIMPID) && + (arch_id != STARFIVE_JH8100_DUBHE80_MARCHID || + impid != STARFIVE_JH8100_DUBHE80_MIMPID)) + return false; + + if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) + return false; + + riscv_cbom_block_size = STARFIVE_JH8100_L3; + riscv_noncoherent_supported(); + + return true; +} + +static u32 starfive_errata_probe(unsigned int stage, + unsigned long archid, unsigned long impid) +{ + u32 cpu_req_errata = 0; + + if (errata_probe_cmo(stage, archid, impid)) + cpu_req_errata |= BIT(ERRATA_STARFIVE_CMO); + + return cpu_req_errata; +} + +void __init_or_module starfive_errata_patch_func(struct alt_entry *begin, + struct alt_entry *end, + unsigned long archid, + unsigned long impid, + unsigned int stage) +{ + struct alt_entry *alt; + u32 cpu_apply_errata = 0; + u32 tmp; + u32 cpu_req_errata; + + if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) + return; + + cpu_req_errata = starfive_errata_probe(stage, archid, impid); + + for (alt = begin; alt < end; alt++) { + if (alt->vendor_id != STARFIVE_VENDOR_ID) + continue; + if (alt->patch_id >= ERRATA_STARFIVE_NUMBER) + continue; + + tmp = (1U << alt->patch_id); + if (cpu_req_errata & tmp) { + mutex_lock(&text_mutex); + patch_text_nosync(ALT_OLD_PTR(alt), ALT_ALT_PTR(alt), + alt->alt_len); + mutex_unlock(&text_mutex); + cpu_apply_errata |= tmp; + } + } + + if (stage != RISCV_ALTERNATIVES_MODULE && + cpu_apply_errata != cpu_req_errata) { + pr_warn("WARNING: Missing StarFive errata patches! \n"); + } +} diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h index 3c2b59b25017..8f5e6883db97 100644 --- a/arch/riscv/include/asm/alternative.h +++ b/arch/riscv/include/asm/alternative.h @@ -51,6 +51,9 @@ void andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, unsigned long archid, unsigned long impid, unsigned int stage); +void starfive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, + unsigned long archid, unsigned long impid, + unsigned int stage); void thead_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, unsigned long archid, unsigned long impid, unsigned int stage); diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index ea33288f8a25..1cd5ba3a1466 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -22,6 +22,11 @@ #define ERRATA_SIFIVE_NUMBER 2 #endif +#ifdef CONFIG_ERRATA_STARFIVE +#define ERRATA_STARFIVE_CMO 0 +#define ERRATA_STARFIVE_NUMBER 1 +#endif + #ifdef CONFIG_ERRATA_THEAD #define ERRATA_THEAD_PBMT 0 #define ERRATA_THEAD_PMU 1 diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c index 319a1da0358b..deedd4b76472 100644 --- a/arch/riscv/kernel/alternative.c +++ b/arch/riscv/kernel/alternative.c @@ -52,6 +52,11 @@ static void riscv_fill_cpu_mfr_info(struct cpu_manufacturer_info_t *cpu_mfr_info cpu_mfr_info->patch_func = sifive_errata_patch_func; break; #endif +#ifdef CONFIG_ERRATA_STARFIVE + case STARFIVE_VENDOR_ID: + cpu_mfr_info->patch_func = starfive_errata_patch_func; + break; +#endif #ifdef CONFIG_ERRATA_THEAD case THEAD_VENDOR_ID: cpu_mfr_info->patch_func = thead_errata_patch_func;