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[v2,3/7] riscv: cpufeature: call match_isa_ext() for single-letter extensions

Message ID 20240314142542.19957-4-andy.chiu@sifive.com (mailing list archive)
State Superseded
Headers show
Series Support Zve32[xf] and Zve64[xfd] Vector subextensions | expand

Checks

Context Check Description
conchuod/vmtest-fixes-PR fail merge-conflict

Commit Message

Andy Chiu March 14, 2024, 2:25 p.m. UTC
Single-letter extensions may also imply multiple subextensions. For
example, Vector extension implies zve64d, and zve64d implies zve64f.

Extension parsing for "riscv,isa-extensions" has the ability to resolve
the dependency by calling match_isa_ext(). This patch makes deprecated
parser call the same function for single letter extensions.

Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
---
 arch/riscv/kernel/cpufeature.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

Comments

Clément Léger March 14, 2024, 3:07 p.m. UTC | #1
On 14/03/2024 15:25, Andy Chiu wrote:
> Single-letter extensions may also imply multiple subextensions. For
> example, Vector extension implies zve64d, and zve64d implies zve64f.
> 
> Extension parsing for "riscv,isa-extensions" has the ability to resolve
> the dependency by calling match_isa_ext(). This patch makes deprecated
> parser call the same function for single letter extensions.
> 
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> ---
>  arch/riscv/kernel/cpufeature.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 36efc8e77ace..d836241a1f11 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -470,6 +470,10 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc
>  
>  		if (unlikely(ext_err))
>  			continue;
> +
> +		for (int i = 0; i < riscv_isa_ext_count; i++)
> +			match_isa_ext(&riscv_isa_ext[i], ext, ext_end, isainfo);
> +
>  		if (!ext_long) {
>  			int nr = tolower(*ext) - 'a';
>  
> @@ -477,9 +481,6 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc
>  				*this_hwcap |= isa2hwcap[nr];
>  				set_bit(nr, isainfo->isa);

Hi Andy,

FWIU, this set_bit() will also be called in match_isa_ext() since it
sets both the "subextensions" bits as well as the "main" extension bit.
So basically, this last "if (!ext_long)" can only set the hwcap bits and
you can remove the set_bit() now that match_isa_ext is called
unconditionally (at least I think so).

Thanks,

Clément

>  			}
> -		} else {
> -			for (int i = 0; i < riscv_isa_ext_count; i++)
> -				match_isa_ext(&riscv_isa_ext[i], ext, ext_end, isainfo);
>  		}
>  	}
>  }
diff mbox series

Patch

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 36efc8e77ace..d836241a1f11 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -470,6 +470,10 @@  static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc
 
 		if (unlikely(ext_err))
 			continue;
+
+		for (int i = 0; i < riscv_isa_ext_count; i++)
+			match_isa_ext(&riscv_isa_ext[i], ext, ext_end, isainfo);
+
 		if (!ext_long) {
 			int nr = tolower(*ext) - 'a';
 
@@ -477,9 +481,6 @@  static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc
 				*this_hwcap |= isa2hwcap[nr];
 				set_bit(nr, isainfo->isa);
 			}
-		} else {
-			for (int i = 0; i < riscv_isa_ext_count; i++)
-				match_isa_ext(&riscv_isa_ext[i], ext, ext_end, isainfo);
 		}
 	}
 }