| Message ID | 20240314142542.19957-6-andy.chiu@sifive.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Support Zve32[xf] and Zve64[xfd] Vector subextensions | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/vmtest-fixes-PR | fail | merge-conflict |
On Thu, Mar 14, 2024, at 10:25 AM, Andy Chiu wrote: > Add description for Zve32x Zve32f Zve64x Zve64f Zve64d ISA extensions. > > Signed-off-by: Andy Chiu <andy.chiu@sifive.com> > --- > Changelog v2: > - new patch since v2 > --- > .../devicetree/bindings/riscv/extensions.yaml | 30 +++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml > b/Documentation/devicetree/bindings/riscv/extensions.yaml > index 63d81dc895e5..6ae50d1227d1 100644 > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > @@ -381,6 +381,36 @@ properties: > instructions, as ratified in commit 56ed795 ("Update > riscv-crypto-spec-vector.adoc") of riscv-crypto. > > + - const: zve32f > + description: > + The standard Zve32f extension for embedded processors, as ratified > + in commit 6f702a2 ("Vector extensions are now ratified") of > + riscv-v-spec. > + > + - const: zve32x > + description: > + The standard Zve32f extension for embedded processors, as ratified Wrong extension name (all except Zve32f). -s > + in commit 6f702a2 ("Vector extensions are now ratified") of > + riscv-v-spec. > + > + - const: zve64x > + description: > + The standard Zve32f extension for embedded processors, as ratified > + in commit 6f702a2 ("Vector extensions are now ratified") of > + riscv-v-spec. > + > + - const: zve64f > + description: > + The standard Zve32f extension for embedded processors, as ratified > + in commit 6f702a2 ("Vector extensions are now ratified") of > + riscv-v-spec. > + > + - const: zve64d > + description: > + The standard Zve32f extension for embedded processors, as ratified > + in commit 6f702a2 ("Vector extensions are now ratified") of > + riscv-v-spec. > + > - const: zvfh > description: > The standard Zvfh extension for vectored half-precision > -- > 2.17.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On 14/03/2024 15:25, Andy Chiu wrote: > Add description for Zve32x Zve32f Zve64x Zve64f Zve64d ISA extensions. > > Signed-off-by: Andy Chiu <andy.chiu@sifive.com> > --- > Changelog v2: > - new patch since v2 Please use scripts/get_maintainers.pl to get a list of necessary people and lists to CC. It might happen, that command when run on an older kernel, gives you outdated entries. Therefore please be sure you base your patches on recent Linux kernel. Tools like b4 or scripts/get_maintainer.pl provide you proper list of people, so fix your workflow. Tools might also fail if you work on some ancient tree (don't, instead use mainline), work on fork of kernel (don't, instead use mainline) or you ignore some maintainers (really don't). Just use b4 and everything should be fine, although remember about `b4 prep --auto-to-cc` if you added new patches to the patchset. You missed at least devicetree list (maybe more), so this won't be tested by automated tooling. Performing review on untested code might be a waste of time, thus I will skip this patch entirely till you follow the process allowing the patch to be tested. Please kindly resend and include all necessary To/Cc entries. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 63d81dc895e5..6ae50d1227d1 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -381,6 +381,36 @@ properties: instructions, as ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. + - const: zve32f + description: + The standard Zve32f extension for embedded processors, as ratified + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + + - const: zve32x + description: + The standard Zve32f extension for embedded processors, as ratified + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + + - const: zve64x + description: + The standard Zve32f extension for embedded processors, as ratified + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + + - const: zve64f + description: + The standard Zve32f extension for embedded processors, as ratified + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + + - const: zve64d + description: + The standard Zve32f extension for embedded processors, as ratified + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + - const: zvfh description: The standard Zvfh extension for vectored half-precision
Add description for Zve32x Zve32f Zve64x Zve64f Zve64d ISA extensions. Signed-off-by: Andy Chiu <andy.chiu@sifive.com> --- Changelog v2: - new patch since v2 --- .../devicetree/bindings/riscv/extensions.yaml | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+)