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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id b19-20020a170906039300b00a442e2940fdsm1735575eja.179.2024.03.15.06.40.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Mar 2024 06:40:13 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, conor.dooley@microchip.com, anup@brainfault.org, atishp@atishpatra.org, christoph.muellner@vrull.eu, heiko@sntech.de, charlie@rivosinc.com, David.Laight@ACULAB.COM Subject: [PATCH 2/5] riscv: Prefer wrs.nto over wrs.sto Date: Fri, 15 Mar 2024 14:40:12 +0100 Message-ID: <20240315134009.580167-9-ajones@ventanamicro.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240315134009.580167-7-ajones@ventanamicro.com> References: <20240315134009.580167-7-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240315_064015_883759_320FCA82 X-CRM114-Status: GOOD ( 10.35 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org When running as a guest we'd like to trap to the host while waiting in order to give the hypervisor a chance to schedule the lock holding VCPU. Unlike wrs.sto, wrs.nto may be configured to raise an exception when its duration expires, so use it instead. Protect ourselves from unhandled exceptions with _ASM_EXTABLE in case the higher privileged level configures wrs.nto to raise exceptions, but then doesn't handle them. Signed-off-by: Andrew Jones --- arch/riscv/include/asm/barrier.h | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 93b3f572d643..441b9eb4b0ef 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -13,6 +13,7 @@ #ifndef __ASSEMBLY__ #include #include +#include #include #include @@ -22,10 +23,14 @@ #define ZAWRS_WRS_NTO ".long 0x00d00073" #define ZAWRS_WRS_STO ".long 0x01d00073" +#define __ALT_WRS_NTO \ + ALTERNATIVE("nop\n", ZAWRS_WRS_NTO "\n", \ + 0, RISCV_ISA_EXT_ZAWRS, CONFIG_RISCV_ISA_ZAWRS) #define ALT_WRS_NTO() \ - __asm__ __volatile__ (ALTERNATIVE( \ - "nop\n", ZAWRS_WRS_NTO "\n", \ - 0, RISCV_ISA_EXT_ZAWRS, CONFIG_RISCV_ISA_ZAWRS)) + __asm__ __volatile__ ( \ + "1: " __ALT_WRS_NTO "\n" \ + "2:\n" \ + _ASM_EXTABLE(1b, 2b)) #define ALT_WRS_STO() \ __asm__ __volatile__ (ALTERNATIVE( \ "nop\n", ZAWRS_WRS_STO "\n", \ @@ -130,7 +135,7 @@ do { \ VAL = __smp_load_reserved_relaxed(__PTR); \ if (cond_expr) \ break; \ - ALT_WRS_STO(); \ + ALT_WRS_NTO(); \ } \ } \ (typeof(*ptr))VAL; \ @@ -147,7 +152,7 @@ do { \ VAL = __smp_load_reserved_acquire(__PTR); \ if (cond_expr) \ break; \ - ALT_WRS_STO(); \ + ALT_WRS_NTO(); \ } \ } \ (typeof(*ptr))VAL; \