From patchwork Mon Mar 18 10:39:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13595208 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 49943C54E5D for ; Mon, 18 Mar 2024 10:40:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=hR3Ia0lUEDK9v2t69WHiUMBKt+Zvge/TI/Mk9+FtGNA=; b=l+qreD/qK7Ull5 4UQqfERktWyS5qYRgEPTx2XiUHpvGBFlJ7vJ9gUWL0D8PRMERFsSr0LD4WNDPkYTnD/jv9NFudmQZ paikuoHaUP2sHGKkiaGvz/gCn9yEi4JBZN1U6auRMXgV9qXxDa68FpsCvnoVB8TuG/OlX03dEo5V0 YshLdU0pFYl9tQP49rOMGs8Rb5/2Jb6ptgN+dX/0sTFcGncZZdQaujrui/AJPa48gVYKsEcQJalz1 eEXqpcUe+LdIk5ixAJKRaBeDgE82inLnJhpyNrMRNjgleW72XqZGJH4TZ3PbvhU3G3ny7nvtEAR5H C48/dMy5oNZomHRWk+sA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rmAPq-00000008B6S-1NXh; Mon, 18 Mar 2024 10:40:27 +0000 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rmAPl-00000008B2j-2Y9W for linux-riscv@lists.infradead.org; Mon, 18 Mar 2024 10:40:24 +0000 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-6e6ee9e3cffso2408542b3a.1 for ; Mon, 18 Mar 2024 03:40:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1710758421; x=1711363221; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=pHRXW9BfVlGJGTuBqz21x9jZhOCb5ENaxkoeEzRsV8g=; b=i8NJWRDSX2uVvDMRTBJvzSE8pWx/wQxB19DDWC8WyHOgVLjacjgXyvAQ9pM5d20wuq VpeH3JVepk0Q2ZEGg7u2Dnl3WVa0ODKHqsuQei7/29l6tpCIuzRd0YdfNAekJe5awSQz 3rjfqIcez/uzQNe7qOlx8eDlbfrKipTHhrvgT4YR4ioyY998TEausVs3wjHGd7lkbwgu RsGrcloZ0IeAcENA/S6eE1iVQv62+FuVI0xJMqvnoVF5DHrDIFknBO403T9kzD/6wGl5 HM0TJx46VzdinXH9UGOaenqOT3vS1YmwvyukDbmxs/G1SocFaO0UPLL3WqiKLFEJRo1x gh1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710758421; x=1711363221; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pHRXW9BfVlGJGTuBqz21x9jZhOCb5ENaxkoeEzRsV8g=; b=g6LE3BFGQin9gXCGYLZw5aZFmfseSeID8CqMbY4ojilrdMlk+f6H9IQNt9FhW6f33I sQaTxTJ9gIuwhYykEb/V3vqhaeA5bMvZ1+qMAF0vJyMALad8egfXsmjvzE3jm7RxTr26 JnfGhrbsYNGJsg4qz1clH5Xn6prdwz3LQArqP8YpLdT/jLEGuooKsiFEndGrT9+yqDxt GAS+HGqlTLWN02ltuOr7ogo3ihUDqqi+DmgaryEImdz3eMNZxNwu0/LrlRQG86riV5JH mQwr5Ww4RYDyTsToC0IdjRDXUUzx6VFBoNFjUsA24bffjO/cmEzkCQ9WdrBtQ1s0RRoh CBsw== X-Gm-Message-State: AOJu0YwTzzz7z+kfrSK1Uuu1r8S7zvF6kp64oGwqXan3TLFdIQsH2zXJ 9If6Cf2pGJXa54M1Zavo7X++KqKgfFbmg0d1E6x+3ASiTzTbjSCBeRRIqD7pW4U= X-Google-Smtp-Source: AGHT+IG9HD964lIVN8dn6HAV4SJOQzPvmgY/XIApnnZHHKJ2o1e4fnnwwXWsSW7pnppyra0VzXddow== X-Received: by 2002:a05:6a00:17a6:b0:6e6:9dfb:7e71 with SMTP id s38-20020a056a0017a600b006e69dfb7e71mr22547429pfg.2.1710758420941; Mon, 18 Mar 2024 03:40:20 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id c11-20020a056a00008b00b006e647716b6esm7838969pfj.149.2024.03.18.03.40.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Mar 2024 03:40:20 -0700 (PDT) From: Andy Chiu Date: Mon, 18 Mar 2024 18:39:59 +0800 Subject: [PATCH v3 6/7] riscv: hwprobe: add zve Vector subextensions into hwprobe interface MIME-Version: 1.0 Message-Id: <20240318-zve-detection-v3-6-e12d42107fa8@sifive.com> References: <20240318-zve-detection-v3-0-e12d42107fa8@sifive.com> In-Reply-To: <20240318-zve-detection-v3-0-e12d42107fa8@sifive.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Andy Chiu , Vincent Chen , Heiko Stuebner , Conor Dooley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Jonathan Corbet Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Greentime Hu , Guo Ren , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, =?utf-8?b?Q2zDqW1l?= =?utf-8?b?bnQgTMOpZ2Vy?= X-Mailer: b4 0.13-dev-a684c X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240318_034021_768971_67DBC924 X-CRM114-Status: GOOD ( 10.85 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The following Vector subextensions for "embedded" platforms are added into RISCV_HWPROBE_KEY_IMA_EXT_0: - ZVE32X - ZVE32F - ZVE64X - ZVE64F - ZVE64D Extensions ending with an X indicates that the platform doesn't have a vector FPU. Extensions ending with F/D mean that whether single (F) or double (D) precision vector operation is supported. The number 32 or 64 follows from ZVE tells the maximum element length. Signed-off-by: Andy Chiu Reviewed-by: Clément Léger --- Changelog v2: - zve* extensions in hwprobe depends on whether kernel supports v, so include them after has_vector(). Fix a typo. (Clément) --- Documentation/arch/riscv/hwprobe.rst | 15 +++++++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 5 +++++ arch/riscv/kernel/sys_hwprobe.c | 5 +++++ 3 files changed, 25 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index b2bcc9eed9aa..d0b02e012e5d 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -188,6 +188,21 @@ The following keys are defined: manual starting from commit 95cf1f9 ("Add changes requested by Ved during signoff") + * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is + supported, as defined by version 1.0 of the RISC-V Vector extension manual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is + supported, as defined by version 1.0 of the RISC-V Vector extension manual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is + supported, as defined by version 1.0 of the RISC-V Vector extension manual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is + supported, as defined by version 1.0 of the RISC-V Vector extension manual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is + supported, as defined by version 1.0 of the RISC-V Vector extension manual. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 9f2a8e3ff204..b9a0876e969f 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -59,6 +59,11 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33) #define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34) #define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35) +#define RISCV_HWPROBE_EXT_ZVE32X (1ULL << 36) +#define RISCV_HWPROBE_EXT_ZVE32F (1ULL << 37) +#define RISCV_HWPROBE_EXT_ZVE64X (1ULL << 38) +#define RISCV_HWPROBE_EXT_ZVE64F (1ULL << 39) +#define RISCV_HWPROBE_EXT_ZVE64D (1ULL << 40) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index 8cae41a502dd..c8219b82fbfc 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -113,6 +113,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZICOND); if (has_vector()) { + EXT_KEY(ZVE32X); + EXT_KEY(ZVE32F); + EXT_KEY(ZVE64X); + EXT_KEY(ZVE64F); + EXT_KEY(ZVE64D); EXT_KEY(ZVBB); EXT_KEY(ZVBC); EXT_KEY(ZVKB);