From patchwork Thu Mar 28 09:18:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 13608258 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 20B26C54E67 for ; Thu, 28 Mar 2024 09:19:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xo4dQaaY5mjTKlivd0JnnoUFO3H5zmJXsfI78VuDeSo=; b=RLMMMiBcfxSE4Y 2arHXCl09wfqAlYQHOC+Vy34nmm278AG/DEUB2tkB5YyW6+bCIspqmrV/ODwPoMfkCrejUaQQRWuJ la1ZnIVxdOtoYNgsloFetXGMXB69TSKaH6BLpIUo0WXnMZ9JfhEAQiq5SOD/iapKnAIOhEfoqXNRe BRvcDy4GvdxCuoFR1TfU/Jx7O4/mKbHSheTnXUl9iUp5DKtLPUl9BVWu//wSsl5OuYTmI6o3HU5AB E7O76vAKFdk5ZD+2o1AXRrwE2tm5ur8x2EvAm6w3SvL0i+ha0F9DaLgwaVk/NeXufGAYIEGzBfV+j gFv9xpeBiHNxD636NZYA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rplv9-0000000DHdC-1107; Thu, 28 Mar 2024 09:19:39 +0000 Received: from mail-sh0chn02on2072b.outbound.protection.partner.outlook.cn ([2406:e500:4420:2::72b] helo=CHN02-SH0-obe.outbound.protection.partner.outlook.cn) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rplug-0000000DHIC-1tNA for linux-riscv@lists.infradead.org; Thu, 28 Mar 2024 09:19:13 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=e9mDw4XwaL2qCTufFfYbS17sAghny7xo91p9nk5lk0l2lUFuX67a1G75h1F35rQpf56Ep1cr6fsrwr3jRHyNw9XOp9mQl1c/gAH1xfmC+vEkf+b2AgDSWohHdlwfD12jPVFHFcWbP9alomLXr3Wb2DJ2tdXOMDpO053d5HnlaPAY5XA3RvHR7cBsM7LLWaTruPHuWF1OG0l8YofacK4oEKAwOVKjVTagTyH72M9NGwSLAQZhzOsdiPOrpA2AOfklxHhAc4IHwycAWAH2M23BUZDeAkT4XS3TmNfS5tLUwUPQ4tpKdSfkb5YOTJ8RO66UKyYJ2tvNmg4xjTH5/LSlCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=e/CTRHF8OXhnsuS900QIctOG+tZySCVcRZiWfg2uaPc=; b=mOU3mUcUSwiFgzQ3aOxKkC8FgkaYQfs08AMvoqFpnUM+IROl1VPKeifTH0fOkXPbdkzdj7FcFwhNGfn/CJs3C0Ma5w4MBqLf/VrUAjRvIgKUQ7R3iIaSpTUDqtzaE2sfy4xVC0F21IrJBcj+ATPlrWM2THmeeUEfsRp9sjNj9gasI+wW0J2svtrPzry01y/u+5SQdraExocMCJxBt1hR17Gt4WAJyvwtoiLX1i0gfCAJAdAgR/GDEgHPL83W+rIw1zD/gUnE88XqDdC3dg2HOpH9ZEqxZDA2ZsDsIjeaTUWteqPU78dPge69UVf98OHJf9smB4vIj7FuECCJQR8k5A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:25::15) by SHXPR01MB0496.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:1f::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7409.32; Thu, 28 Mar 2024 09:18:48 +0000 Received: from SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn ([fe80::c738:9e6b:f92e:8bb9]) by SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn ([fe80::c738:9e6b:f92e:8bb9%6]) with mapi id 15.20.7409.031; Thu, 28 Mar 2024 09:18:48 +0000 From: Minda Chen To: Lorenzo Pieralisi , Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Thomas Gleixner , Daire McNamara , Emil Renner Berthing , Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-pci@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v16 04/22] PCI: microchip: Add bridge_addr field to struct mc_pcie Date: Thu, 28 Mar 2024 17:18:17 +0800 Message-Id: <20240328091835.14797-5-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240328091835.14797-1-minda.chen@starfivetech.com> References: <20240328091835.14797-1-minda.chen@starfivetech.com> X-ClientProxiedBy: NT0PR01CA0020.CHNPR01.prod.partner.outlook.cn (2406:e500:c510:c::16) To SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:25::15) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SHXPR01MB0863:EE_|SHXPR01MB0496:EE_ X-MS-Office365-Filtering-Correlation-Id: 1531236a-9d19-4211-6dec-08dc4f081319 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4m4Fsdzby4aHg6pwz3IWaXSLKZIhQObJ3Z0DA/3a9DiDu/HS9lCLh74WuWlYLCCr10hH32DE8SDv+2aNrKgnMQFXYn/rBmv4dW44U3iMDdTivCB06cnOdgw7piv/W06HiJ/raWVUxacbrm897DbKtmOXJkNGY2/Nab3ZQpQ54NfIyvK4frd82VDi5daiifuAXYhzQH8X5yWW5ISTgtRj+GHEZdvK9SPKt0eDBWgundAzUNyg2wsx3ah2gFuzShgOhuImd5A0mOCQTP8F94eagTw6efFLtdAiSVfYqinxAVLKNNSm6MCixXIha6IGlUu2ieXJZ8C0cRckRYoJ/4bsG4t1fFlj3VWT1fJVtoErguwHyLQVVnB9XyEjRAQAVfBGWF4E23v8OdMQauQpQy17+iCP8/JAPSFem9jsgxpIUnYLM/QbUCqOJPy7Sqs5OQwWfC1CgTEtlDRhC36v2oobXErWcqb8Hu3UdfxwY7ahxLeoCk7oahMFhdvm9s31XExld88ZqapfI6gSacceLVZKVxI1E2tAkN0BJvCQIW8pcS8EXmL4JPXrY9qGgnfjnfMpKe72S/sgHRiWx1V8iJYhvRF79gf4DAbisDHntvJLaKunKnbDnjBDxl0YKt5YZdjC X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn;PTR:;CAT:NONE;SFS:(13230031)(52116005)(1800799015)(7416005)(41320700004)(366007)(38350700005);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: LEP7CU1dKkthXxiP42OrVoaHH0lnkRudwzyiUW12FVOPJu0j9OQG4yAWmm7gWDyqq0+ehRsXHGvQSewc3CZgvxYiyE4AGDQPW3u0XlNCU/ZRIBNWiYtxeQGZmC4Uk0Gm/ZY61ET7s+5X1ExsAgbQ65s6Delj2Z9UBrw2Ss1ruUu7gEl/2RNt+XoLrSfwx+buaWE3uMrMQigqGi+j3wUpLrMFzsAeSi/sbAiNaW8lnhgSPsSWHsY2JDJ4qYAoJHAvQsJHswVvbwu9zS25xBptpDsU1H8YEZ/b1pNyEe40bAJbwHDU9UwraFRGGiBay1VI94Oe8l6WSGbMDcANRgBdssP9r7rMtSJXRKpNVE25968oi7IQTK6Vk/8CItxFK9LoVIviYPqhZLk3Px8AVfY8OYJDM42N7/fWTcP3OTGrfbNztcFQ92OmzF92V1wLDeHgOVCsTBM4Cz1nQWHaNdEJbRQzEFQ+v2Zl56R9BjBezw5fELuZhV77eDcobWf2ayqeAB5O+RDKo91EGUt1hME0/epp1ORK+aJsh5xE+UJpDxqxva7Hf0uO+Akn0wXixk5GPxLwEvtTExVdFMQTGYFml+UAiy4h1NEkwQ9tS/wNicPYPDT07reZlRAIk7rXLuNMYCx1lmQ1WrSbygnqJKjnC/SrQJzDVijhJa5gB7JKIf2zAPBtuImIvK2jFvIbvlUuqhE8jjyuOtLbIeOSngSEIx7NKfBEPdkvL0RDm5he9LDfK4YOr43PV3I2hW7MF4wnUeFlxbrIAVTjDhIvhsW/BDdu/fd1KR4W4D8xiwhhA+5uJkyJS3JarrP4BTN/QVDG6719g1Ct3RbLCr9ZlGrV6vPiSvoAdkNCTJZOeuuyGJdsKzvxAHbB3qtwTjTk3x0WLV46tF09rmmzdlKAAqIwSICyBMXtElmcMjhdU/5l//C7MS98UWfao/L9w2+y+xYmFbibcin7JB3twI5iq86L1YpaTapCwMToVrh+E9R31amwrnGUXeOwqpMOTOWd4obCvJtBEmY0JZEghNWyuU5fKG1PlC0tmF4+dPg7ONOTtMpbF3ujSMwwLBWQokeK4zbIhc7220h3+vFPKYa1EVihKMe4jZpUyFg9tDNSZH2SwCz/pXC9JaUKYNjM0Cx1mI3QFgawoz+j4TkXOV2xkzMLfXNcKhOCbKqc38h5mUsVpcEXvPRn7uA1m3FJd2P+i04QJA91HIlSGnH5lvWHWbHDKTN7md79IYUPAaC67Tobp+/CB9rrKRopaynyf1PKPtFcHzDYQ4NKEY/6W5T8JJTQ8YIYIs1JbXLlxdQJXI4/41tZhup7l5vociEa0BhS+Uy2TaUBuZTXKa1TtwjucrUBBHT6agFwioCYaRAS672YeUJuCoBq83fezEePf3p2/DPlsEVKFyeQdEuyL15oQ/v+gPnZMHKjlcmTT+/vgyQXyAlurmvJkm38jmYxUPr9PCR7wOJvOKC29BlvOhe5N7/fBVxTGolL0WABNmFNbhrO4Fp9Xi5dMCiAzZMgxNoy1yz2jxRQWm8u0qVl5xp1xqrE/BPlMtCcBJNcz/9sjXUmKUSnHQKmIkItZ0Gc6zGcsCKJd1Zuds9IsDaERE0wMRn1Jg== X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1531236a-9d19-4211-6dec-08dc4f081319 X-MS-Exchange-CrossTenant-AuthSource: SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Mar 2024 09:18:47.9642 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Gf84FnfnzkpyIrmswrcBLts8mO6yyTzHR5G5q0UeeXUlZmKrreFUeANWOiyHY/Shg2WF9+71H/72+xy0qF8RrBkmZyzGro8SDmBLfJ5X/Vg= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SHXPR01MB0496 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240328_021910_683761_97F4A573 X-CRM114-Status: GOOD ( 12.48 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Bridge address base is common PLDA field, add this to struct mc_pcie first. INTx and MSI interrupt code will be changed to common code, so get the bridge base address from port->bridge_addr instead of axi_base_addr. axi_base_addr is Microchip its own data. Signed-off-by: Minda Chen Reviewed-by: Conor Dooley --- .../pci/controller/plda/pcie-microchip-host.c | 23 ++++++++----------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index d9030d550482..c55ede80a6d0 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -195,6 +195,7 @@ struct mc_pcie { struct irq_domain *event_domain; raw_spinlock_t lock; struct mc_msi msi; + void __iomem *bridge_addr; }; struct cause { @@ -339,8 +340,7 @@ static void mc_handle_msi(struct irq_desc *desc) struct irq_chip *chip = irq_desc_get_chip(desc); struct device *dev = port->dev; struct mc_msi *msi = &port->msi; - void __iomem *bridge_base_addr = - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; + void __iomem *bridge_base_addr = port->bridge_addr; unsigned long status; u32 bit; int ret; @@ -365,8 +365,7 @@ static void mc_handle_msi(struct irq_desc *desc) static void mc_msi_bottom_irq_ack(struct irq_data *data) { struct mc_pcie *port = irq_data_get_irq_chip_data(data); - void __iomem *bridge_base_addr = - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; + void __iomem *bridge_base_addr = port->bridge_addr; u32 bitpos = data->hwirq; writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI); @@ -488,8 +487,7 @@ static void mc_handle_intx(struct irq_desc *desc) struct mc_pcie *port = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); struct device *dev = port->dev; - void __iomem *bridge_base_addr = - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; + void __iomem *bridge_base_addr = port->bridge_addr; unsigned long status; u32 bit; int ret; @@ -514,8 +512,7 @@ static void mc_handle_intx(struct irq_desc *desc) static void mc_ack_intx_irq(struct irq_data *data) { struct mc_pcie *port = irq_data_get_irq_chip_data(data); - void __iomem *bridge_base_addr = - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; + void __iomem *bridge_base_addr = port->bridge_addr; u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL); @@ -524,8 +521,7 @@ static void mc_ack_intx_irq(struct irq_data *data) static void mc_mask_intx_irq(struct irq_data *data) { struct mc_pcie *port = irq_data_get_irq_chip_data(data); - void __iomem *bridge_base_addr = - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; + void __iomem *bridge_base_addr = port->bridge_addr; unsigned long flags; u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); u32 val; @@ -540,8 +536,7 @@ static void mc_mask_intx_irq(struct irq_data *data) static void mc_unmask_intx_irq(struct irq_data *data) { struct mc_pcie *port = irq_data_get_irq_chip_data(data); - void __iomem *bridge_base_addr = - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; + void __iomem *bridge_base_addr = port->bridge_addr; unsigned long flags; u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); u32 val; @@ -896,8 +891,7 @@ static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, static int mc_pcie_setup_windows(struct platform_device *pdev, struct mc_pcie *port) { - void __iomem *bridge_base_addr = - port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; + void __iomem *bridge_base_addr = port->bridge_addr; struct pci_host_bridge *bridge = platform_get_drvdata(pdev); struct resource_entry *entry; u64 pci_addr; @@ -1081,6 +1075,7 @@ static int mc_host_probe(struct platform_device *pdev) mc_disable_interrupts(port); bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; + port->bridge_addr = bridge_base_addr; /* Allow enabling MSI by disabling MSI-X */ val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0);