| Message ID | 20240409061043.3269676-4-debug@rivosinc.com (mailing list archive) |
|---|---|
| State | RFC |
| Headers | show |
| Series | [RFC,01/12] riscv: zicfiss / zicfilp extension csr and bit definitions | expand |
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 68a24cf9481a..be07355b9eff 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -56,7 +56,7 @@ SYM_CODE_START(handle_exception) * Disable the FPU/Vector to detect illegal usage of floating point * or vector in kernel space. */ - li t0, SR_SUM | SR_FS_VS + li t0, SR_SUM | SR_FS_VS | SR_ELP REG_L s0, TASK_TI_USER_SP(tp) csrrc s1, CSR_STATUS, t0
On trap entry, save expected landing pad state and subsequently clear it in sstatus so that if there are traps later on in kernel and sret happens back to same mode, cpu will start faulting. Signed-off-by: Deepak Gupta <debug@rivosinc.com> --- arch/riscv/kernel/entry.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)