Message ID | 20240414025826.64025-3-cuiyunhui@bytedance.com (mailing list archive) |
---|---|
State | Superseded |
Headers | show
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Sat, 13 Apr 2024 19:59:49 -0700 (PDT) Received: from L6YN4KR4K9.bytedance.net ([139.177.225.246]) by smtp.gmail.com with ESMTPSA id cx15-20020a17090afd8f00b002a219f8079fsm4799913pjb.33.2024.04.13.19.59.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 13 Apr 2024 19:59:49 -0700 (PDT) From: Yunhui Cui <cuiyunhui@bytedance.com> To: rafael@kernel.org, lenb@kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org, bhelgaas@google.com, james.morse@arm.com, jhugo@codeaurora.org, jeremy.linton@arm.com, john.garry@huawei.com, Jonathan.Cameron@huawei.com, pierre.gondois@arm.com, sudeep.holla@arm.com, tiantao6@huawei.com Cc: Yunhui Cui <cuiyunhui@bytedance.com> Subject: [PATCH v2 3/3] RISC-V: Select ACPI PPTT drivers Date: Sun, 14 Apr 2024 10:58:26 +0800 Message-Id: <20240414025826.64025-3-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20240414025826.64025-1-cuiyunhui@bytedance.com> References: <20240414025826.64025-1-cuiyunhui@bytedance.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240413_195951_275536_BC7841BC X-CRM114-Status: UNSURE ( 7.05 ) X-CRM114-Notice: Please train this message. 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Series |
[v2,1/3] riscv: cacheinfo: remove the useless parameter (node) of ci_leaf_init()
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diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6d64888134ba..5d73fcaf9136 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -14,6 +14,7 @@ config RISCV def_bool y select ACPI_GENERIC_GSI if ACPI select ACPI_REDUCED_HARDWARE_ONLY if ACPI + select ACPI_PPTT if ACPI select ARCH_DMA_DEFAULT_COHERENT select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
After adding ACPI support to populate_cache_leaves(), RISC-V can build cacheinfo through the ACPI PPTT table, thus enabling the ACPI_PPTT configuration. Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com> --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+)