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All other PMU events are unchanged from earlier Bullet cores. Signed-off-by: Eric Lin Co-developed-by: Samuel Holland Signed-off-by: Samuel Holland --- tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 + .../cycle-and-instruction-count.json | 12 ++++ .../arch/riscv/sifive/bullet-07/firmware.json | 1 + .../riscv/sifive/bullet-07/instruction.json | 1 + .../arch/riscv/sifive/bullet-07/memory.json | 1 + .../riscv/sifive/bullet-07/microarch.json | 62 +++++++++++++++++++ .../riscv/sifive/bullet-07/watchpoint.json | 42 +++++++++++++ 7 files changed, 120 insertions(+) create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv index 521f416b0006..8706d289215e 100644 --- a/tools/perf/pmu-events/arch/riscv/mapfile.csv +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv @@ -15,6 +15,7 @@ # #MVENDORID-MARCHID-MIMPID,Version,Filename,EventType 0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/bullet,core +0x489-0x8000000000000[1-9a-e]07-0x[78ac][[:xdigit:]]+,v1,sifive/bullet-07,core 0x5b7-0x0-0x0,v1,thead/c900-legacy,core 0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core 0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json new file mode 100644 index 000000000000..5c8124cfe926 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json @@ -0,0 +1,12 @@ +[ + { + "EventName": "CORE_CLOCK_CYCLES", + "EventCode": "0x165", + "BriefDescription": "Counts core clock cycles" + }, + { + "EventName": "INSTRUCTIONS_RETIRED", + "EventCode": "0x265", + "BriefDescription": "Counts instructions retired" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json new file mode 120000 index 000000000000..34e5c2870eee --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json @@ -0,0 +1 @@ +../bullet/firmware.json \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json new file mode 120000 index 000000000000..62eacc2d7497 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json @@ -0,0 +1 @@ +../bullet/instruction.json \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json new file mode 120000 index 000000000000..df50fc47a5fe --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json @@ -0,0 +1 @@ +../bullet/memory.json \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json new file mode 100644 index 000000000000..de8efd7b8b34 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json @@ -0,0 +1,62 @@ +[ + { + "EventName": "ADDRESSGEN_INTERLOCK", + "EventCode": "0x101", + "BriefDescription": "Counts cycles with an address-generation interlock" + }, + { + "EventName": "LONGLATENCY_INTERLOCK", + "EventCode": "0x201", + "BriefDescription": "Counts cycles with a long-latency interlock" + }, + { + "EventName": "CSR_INTERLOCK", + "EventCode": "0x401", + "BriefDescription": "Counts cycles with a CSR interlock" + }, + { + "EventName": "ICACHE_BLOCKED", + "EventCode": "0x801", + "BriefDescription": "Counts cycles in which the instruction cache was not able to provide an instruction" + }, + { + "EventName": "DCACHE_BLOCKED", + "EventCode": "0x1001", + "BriefDescription": "Counts cycles in which the data cache blocked an instruction" + }, + { + "EventName": "BRANCH_DIRECTION_MISPREDICTION", + "EventCode": "0x2001", + "BriefDescription": "Counts mispredictions of conditional branch direction (taken/not taken)" + }, + { + "EventName": "BRANCH_TARGET_MISPREDICTION", + "EventCode": "0x4001", + "BriefDescription": "Counts mispredictions of the target PC of control-flow instructions" + }, + { + "EventName": "PIPELINE_FLUSH", + "EventCode": "0x8001", + "BriefDescription": "Counts flushes of the core pipeline. Common causes include fence.i and CSR accesses" + }, + { + "EventName": "REPLAY", + "EventCode": "0x10001", + "BriefDescription": "Counts instruction replays" + }, + { + "EventName": "INTEGER_MUL_DIV_INTERLOCK", + "EventCode": "0x20001", + "BriefDescription": "Counts cycles with a multiply or divide interlock" + }, + { + "EventName": "FP_INTERLOCK", + "EventCode": "0x40001", + "BriefDescription": "Counts cycles with a floating-point interlock" + }, + { + "EventName": "TRACE_STALL", + "EventCode": "0x80001", + "BriefDescription": "Counts cycles in which the core pipeline is stalled due to backpressure from the Trace Encoder" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json new file mode 100644 index 000000000000..aa7a12818521 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json @@ -0,0 +1,42 @@ +[ + { + "EventName": "WATCHPOINT_0", + "EventCode": "0x164", + "BriefDescription": "Counts occurrences of watchpoint 0 with action=8" + }, + { + "EventName": "WATCHPOINT_1", + "EventCode": "0x264", + "BriefDescription": "Counts occurrences of watchpoint 1 with action=8" + }, + { + "EventName": "WATCHPOINT_2", + "EventCode": "0x464", + "BriefDescription": "Counts occurrences of watchpoint 2 with action=8" + }, + { + "EventName": "WATCHPOINT_3", + "EventCode": "0x864", + "BriefDescription": "Counts occurrences of watchpoint 3 with action=8" + }, + { + "EventName": "WATCHPOINT_4", + "EventCode": "0x1064", + "BriefDescription": "Counts occurrences of watchpoint 4 with action=8" + }, + { + "EventName": "WATCHPOINT_5", + "EventCode": "0x2064", + "BriefDescription": "Counts occurrences of watchpoint 5 with action=8" + }, + { + "EventName": "WATCHPOINT_6", + "EventCode": "0x4064", + "BriefDescription": "Counts occurrences of watchpoint 6 with action=8" + }, + { + "EventName": "WATCHPOINT_7", + "EventCode": "0x8064", + "BriefDescription": "Counts occurrences of watchpoint 7 with action=8" + } +]