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AJvYcCVl3yeYyHTy/uaAgwITOkFI2CEwD2FqrL0U/Do7ohlVJCusvlT9JItNaCKwecLbiXu0lUiRSQlYKmd5SHVIOn/BDIyxzRuPtXZXg2rLKSmu X-Gm-Message-State: AOJu0YxIIJnnFCFDDYf0NHezBXOkcm3glJzsVKBRIe+J3SHSV21AR5oJ ja/dzTEFdqRiljVCtxA3+NIIp38f71cpUgHhHA5yuo3jzVjcZKhaLCLSoiXkmDo= X-Google-Smtp-Source: AGHT+IE9ZoyucFXxbdSGw7XJTOvvL/daIX0wCHcvpRgNlMZzb6xM1tdXMzrCLA56bysKpPynTf/B8w== X-Received: by 2002:a17:902:f548:b0:1e5:8629:44d with SMTP id d9443c01a7336-1eeb03a6a1dmr52745165ad.1.1715220941080; Wed, 08 May 2024 19:15:41 -0700 (PDT) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0b9d176fsm2339115ad.58.2024.05.08.19.15.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 May 2024 19:15:40 -0700 (PDT) From: Samuel Holland To: Arnaldo Carvalho de Melo , Palmer Dabbelt , linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Mark Rutland , Adrian Hunter , Alexander Shishkin , Jiri Olsa , Peter Zijlstra , Ingo Molnar , Ian Rogers , Namhyung Kim , Arnaldo Carvalho de Melo , Eric Lin , Samuel Holland Subject: [PATCH 5/7] perf vendor events riscv: Add SiFive Bullet version 0x0d events Date: Wed, 8 May 2024 19:14:58 -0700 Message-ID: <20240509021531.680920-6-samuel.holland@sifive.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240509021531.680920-1-samuel.holland@sifive.com> References: <20240509021531.680920-1-samuel.holland@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240508_191543_223755_44D5F07A X-CRM114-Status: GOOD ( 16.59 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Eric Lin SiFive Bullet microarchitecture cores with mimpid values starting with 0x0d or greater add new PMU events to count TLB miss stall cycles. All other PMU events are unchanged from earlier Bullet cores. Signed-off-by: Eric Lin Signed-off-by: Samuel Holland --- tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 + .../cycle-and-instruction-count.json | 1 + .../arch/riscv/sifive/bullet-0d/firmware.json | 1 + .../riscv/sifive/bullet-0d/instruction.json | 1 + .../arch/riscv/sifive/bullet-0d/memory.json | 1 + .../riscv/sifive/bullet-0d/microarch.json | 72 +++++++++++++++++++ .../riscv/sifive/bullet-0d/watchpoint.json | 1 + 7 files changed, 78 insertions(+) create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv index 8706d289215e..9e9bd7ac0ebe 100644 --- a/tools/perf/pmu-events/arch/riscv/mapfile.csv +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv @@ -16,6 +16,7 @@ #MVENDORID-MARCHID-MIMPID,Version,Filename,EventType 0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/bullet,core 0x489-0x8000000000000[1-9a-e]07-0x[78ac][[:xdigit:]]+,v1,sifive/bullet-07,core +0x489-0x8000000000000[1-9a-e]07-0xd[[:xdigit:]]+,v1,sifive/bullet-0d,core 0x5b7-0x0-0x0,v1,thead/c900-legacy,core 0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core 0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json new file mode 120000 index 000000000000..ccd29278f61b --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json @@ -0,0 +1 @@ +../bullet-07/cycle-and-instruction-count.json \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json new file mode 120000 index 000000000000..34e5c2870eee --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json @@ -0,0 +1 @@ +../bullet/firmware.json \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json new file mode 120000 index 000000000000..62eacc2d7497 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json @@ -0,0 +1 @@ +../bullet/instruction.json \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json new file mode 120000 index 000000000000..df50fc47a5fe --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json @@ -0,0 +1 @@ +../bullet/memory.json \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json new file mode 100644 index 000000000000..6573b24788eb --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json @@ -0,0 +1,72 @@ +[ + { + "EventName": "ADDRESSGEN_INTERLOCK", + "EventCode": "0x101", + "BriefDescription": "Counts cycles with an address-generation interlock" + }, + { + "EventName": "LONGLATENCY_INTERLOCK", + "EventCode": "0x201", + "BriefDescription": "Counts cycles with a long-latency interlock" + }, + { + "EventName": "CSR_INTERLOCK", + "EventCode": "0x401", + "BriefDescription": "Counts cycles with a CSR interlock" + }, + { + "EventName": "ICACHE_BLOCKED", + "EventCode": "0x801", + "BriefDescription": "Counts cycles in which the instruction cache was not able to provide an instruction" + }, + { + "EventName": "DCACHE_BLOCKED", + "EventCode": "0x1001", + "BriefDescription": "Counts cycles in which the data cache blocked an instruction" + }, + { + "EventName": "BRANCH_DIRECTION_MISPREDICTION", + "EventCode": "0x2001", + "BriefDescription": "Counts mispredictions of conditional branch direction (taken/not taken)" + }, + { + "EventName": "BRANCH_TARGET_MISPREDICTION", + "EventCode": "0x4001", + "BriefDescription": "Counts mispredictions of the target PC of control-flow instructions" + }, + { + "EventName": "PIPELINE_FLUSH", + "EventCode": "0x8001", + "BriefDescription": "Counts flushes of the core pipeline. Common causes include fence.i and CSR accesses" + }, + { + "EventName": "REPLAY", + "EventCode": "0x10001", + "BriefDescription": "Counts instruction replays" + }, + { + "EventName": "INTEGER_MUL_DIV_INTERLOCK", + "EventCode": "0x20001", + "BriefDescription": "Counts cycles with a multiply or divide interlock" + }, + { + "EventName": "FP_INTERLOCK", + "EventCode": "0x40001", + "BriefDescription": "Counts cycles with a floating-point interlock" + }, + { + "EventName": "TRACE_STALL", + "EventCode": "0x80001", + "BriefDescription": "Counts cycles in which the core pipeline is stalled due to backpressure from the Trace Encoder" + }, + { + "EventName": "ITLB_MISS_STALL", + "EventCode": "0x100001", + "BriefDescription": "Counts cycles in which the core pipeline is stalled due to ITLB Miss" + }, + { + "EventName": "DTLB_MISS_STALL", + "EventCode": "0x200001", + "BriefDescription": "Counts cycles in which the core pipeline is stalled due to DTLB Miss" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json new file mode 120000 index 000000000000..e88b98bfc5c8 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json @@ -0,0 +1 @@ +../bullet-07/watchpoint.json \ No newline at end of file