| Message ID | 20240527092405.134967-1-dqfext@gmail.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 93b63f68d00a0483b450b446e2ea5386a1b94213 |
| Headers | show |
| Series | [v2] riscv: lib: relax assembly constraints in hweight | expand |
> -----Original Message----- > From: Qingfang Deng <dqfext@gmail.com> > Sent: Monday, May 27, 2024 5:24 PM > To: Paul Walmsley <paul.walmsley@sifive.com>; Palmer Dabbelt > <palmer@dabbelt.com>; Albert Ou <aou@eecs.berkeley.edu>; linux- > riscv@lists.infradead.org; linux-kernel@vger.kernel.org > Cc: Wang, Xiao W <xiao.w.wang@intel.com>; Qingfang Deng > <qingfang.deng@siflower.com.cn> > Subject: [PATCH v2] riscv: lib: relax assembly constraints in hweight > > From: Qingfang Deng <qingfang.deng@siflower.com.cn> > > rd and rs don't have to be the same. In some cases where rs needs to be > saved for later usage, this will save us some mv instructions. > > Signed-off-by: Qingfang Deng <qingfang.deng@siflower.com.cn> > --- > v2: updated title as suggested by Xiao. > > arch/riscv/include/asm/arch_hweight.h | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/riscv/include/asm/arch_hweight.h > b/arch/riscv/include/asm/arch_hweight.h > index 85b2c443823e..613769b9cdc9 100644 > --- a/arch/riscv/include/asm/arch_hweight.h > +++ b/arch/riscv/include/asm/arch_hweight.h > @@ -26,9 +26,9 @@ static __always_inline unsigned int > __arch_hweight32(unsigned int w) > > asm (".option push\n" > ".option arch,+zbb\n" > - CPOPW "%0, %0\n" > + CPOPW "%0, %1\n" > ".option pop\n" > - : "+r" (w) : :); > + : "=r" (w) : "r" (w) :); > > return w; > > @@ -57,9 +57,9 @@ static __always_inline unsigned long > __arch_hweight64(__u64 w) > > asm (".option push\n" > ".option arch,+zbb\n" > - "cpop %0, %0\n" > + "cpop %0, %1\n" > ".option pop\n" > - : "+r" (w) : :); > + : "=r" (w) : "r" (w) :); > > return w; > > -- > 2.34.1 Reviewed-by: Xiao Wang <xiao.w.wang@intel.com>
Hello: This patch was applied to riscv/linux.git (for-next) by Palmer Dabbelt <palmer@rivosinc.com>: On Mon, 27 May 2024 17:24:04 +0800 you wrote: > From: Qingfang Deng <qingfang.deng@siflower.com.cn> > > rd and rs don't have to be the same. In some cases where rs needs to be > saved for later usage, this will save us some mv instructions. > > Signed-off-by: Qingfang Deng <qingfang.deng@siflower.com.cn> > > [...] Here is the summary with links: - [v2] riscv: lib: relax assembly constraints in hweight https://git.kernel.org/riscv/c/93b63f68d00a You are awesome, thank you!
diff --git a/arch/riscv/include/asm/arch_hweight.h b/arch/riscv/include/asm/arch_hweight.h index 85b2c443823e..613769b9cdc9 100644 --- a/arch/riscv/include/asm/arch_hweight.h +++ b/arch/riscv/include/asm/arch_hweight.h @@ -26,9 +26,9 @@ static __always_inline unsigned int __arch_hweight32(unsigned int w) asm (".option push\n" ".option arch,+zbb\n" - CPOPW "%0, %0\n" + CPOPW "%0, %1\n" ".option pop\n" - : "+r" (w) : :); + : "=r" (w) : "r" (w) :); return w; @@ -57,9 +57,9 @@ static __always_inline unsigned long __arch_hweight64(__u64 w) asm (".option push\n" ".option arch,+zbb\n" - "cpop %0, %0\n" + "cpop %0, %1\n" ".option pop\n" - : "+r" (w) : :); + : "=r" (w) : "r" (w) :); return w;