| Message ID | 20240531100407.282-1-dqfext@gmail.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | RISC-V: Implement ioremap_wc/wt | expand |
Hi Qingfang, On Fri, May 31, 2024 at 6:04 PM Qingfang Deng <dqfext@gmail.com> wrote: > > From: Qingfang Deng <qingfang.deng@siflower.com.cn> > > Currently on RISC-V, ioremap_wc/wt uses the default ioremap > implementation, which maps the memory as strongly-ordered non-cacheable > IO memory on systems with Svpbmt. > > To improve performance, map the memory as weakly-ordered non-cacheable > normal memory. > > Signed-off-by: Qingfang Deng <qingfang.deng@siflower.com.cn> > --- > arch/riscv/include/asm/io.h | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h > index 1c5c641075d2..582503e0f508 100644 > --- a/arch/riscv/include/asm/io.h > +++ b/arch/riscv/include/asm/io.h > @@ -133,6 +133,14 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw()) > #define outsq(addr, buffer, count) __outsq(PCI_IOBASE + (addr), buffer, count) > #endif > > +#ifdef CONFIG_MMU > +#define ioremap_wc(addr, size) \ > + ioremap_prot((addr), (size), \ > + (_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_NOCACHE) > + > +#define ioremap_wt ioremap_wc > +#endif > + > #include <asm-generic/io.h> > > #ifdef CONFIG_MMU > -- > 2.34.1 > > Can you provide specific test data for performance improvement? Thanks, Yunhui
diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 1c5c641075d2..582503e0f508 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -133,6 +133,14 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw()) #define outsq(addr, buffer, count) __outsq(PCI_IOBASE + (addr), buffer, count) #endif +#ifdef CONFIG_MMU +#define ioremap_wc(addr, size) \ + ioremap_prot((addr), (size), \ + (_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_NOCACHE) + +#define ioremap_wt ioremap_wc +#endif + #include <asm-generic/io.h> #ifdef CONFIG_MMU