| Message ID | 20240612-sg2002-v2-5-19a585af6846@bootlin.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add board support for Sipeed LicheeRV Nano | expand |
Hi Thomas, On 2024-06-12 3:02 AM, Thomas Bonnefille wrote: > Add initial device tree for the SG2002 RISC-V SoC by SOPHGO. > > Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com> > --- > arch/riscv/boot/dts/sophgo/sg2002.dtsi | 34 ++++++++++++++++++++++++++++++++++ > 1 file changed, 34 insertions(+) > > diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/dts/sophgo/sg2002.dtsi > new file mode 100644 > index 000000000000..0fc80da7c139 > --- /dev/null > +++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi > @@ -0,0 +1,34 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com> > + */ > + > +/dts-v1/; While it doesn't hurt, you don't need this directive in both the .dtsi and each .dts file. It looks like it usually goes in the board .dts file only. Regards, Samuel > + > +#include <dt-bindings/interrupt-controller/irq.h> > +#include "cv18xx.dtsi" > + > +/ { > + compatible = "sophgo,sg2002"; > + > + memory@80000000 { > + device_type = "memory"; > + reg = <0x80000000 0x10000000>; > + }; > +}; > + > +&plic { > + compatible = "sophgo,sg2002-plic", "thead,c900-plic"; > +}; > + > +&clint { > + compatible = "sophgo,sg2002-clint", "thead,c900-clint"; > +}; > + > +&clk { > + compatible = "sophgo,sg2000-clk"; > +}; > + > +&sdhci0 { > + compatible = "sophgo,sg2002-dwcmshc"; > +}; >
diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/dts/sophgo/sg2002.dtsi new file mode 100644 index 000000000000..0fc80da7c139 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com> + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/irq.h> +#include "cv18xx.dtsi" + +/ { + compatible = "sophgo,sg2002"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; +}; + +&plic { + compatible = "sophgo,sg2002-plic", "thead,c900-plic"; +}; + +&clint { + compatible = "sophgo,sg2002-clint", "thead,c900-clint"; +}; + +&clk { + compatible = "sophgo,sg2000-clk"; +}; + +&sdhci0 { + compatible = "sophgo,sg2002-dwcmshc"; +};
Add initial device tree for the SG2002 RISC-V SoC by SOPHGO. Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com> --- arch/riscv/boot/dts/sophgo/sg2002.dtsi | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+)