| Message ID | 20240613191616.2101821-2-jesse@rivosinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | RISC-V: Detect and report speed of unaligned vector accesses | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/vmtest-fixes-PR | fail | merge-conflict |
On Thu, Jun 13, 2024 at 03:16:10PM -0400, Jesse Taube wrote: > > Zicclsm Misaligned loads and stores to main memory regions with both > > the cacheability and coherence PMAs must be supported. > > Note: > > This introduces a new extension name for this feature. > > This requires misaligned support for all regular load and store > > instructions (including scalar and vector) but not AMOs or other > > specialized forms of memory access. Even though mandated, misaligned > > loads and stores might execute extremely slowly. Standard software > > distributions should assume their existence only for correctness, > > not for performance. > > Detecing zicclsm allows the kernel to report if the > hardware supports misaligned accesses even if support wasn't probed. > > This is useful for usermode to know if vector misaligned accesses are > supported. > > Signed-off-by: Jesse Taube <jesse@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
On Fri, Jun 14, 2024 at 4:09 PM Conor Dooley <conor.dooley@microchip.com> wrote: > > On Thu, Jun 13, 2024 at 03:16:10PM -0400, Jesse Taube wrote: > > > Zicclsm Misaligned loads and stores to main memory regions with both > > > the cacheability and coherence PMAs must be supported. > > > Note: > > > This introduces a new extension name for this feature. > > > This requires misaligned support for all regular load and store > > > instructions (including scalar and vector) but not AMOs or other > > > specialized forms of memory access. Even though mandated, misaligned > > > loads and stores might execute extremely slowly. Standard software > > > distributions should assume their existence only for correctness, > > > not for performance. > > > > Detecing zicclsm allows the kernel to report if the > > hardware supports misaligned accesses even if support wasn't probed. > > > > This is useful for usermode to know if vector misaligned accesses are > > supported. > > > > Signed-off-by: Jesse Taube <jesse@rivosinc.com> > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Andy Chiu <andy.chiu@sifive.com>
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index df5045103e73..7085a694b801 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -207,6 +207,9 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is supported, as defined by version 1.0 of the RISC-V Vector extension manual. + * :c:macro:`RISCV_HWPROBE_EXT_ZICCLSM`: The Zicclsm extension is supported as + defined in the RISC-V RVA Profiles Specification. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_PERF`, but the key was mistakenly classified as a bitmask rather than a value. diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index f64d4e98e67c..0b3bd8885a2b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -86,6 +86,7 @@ #define RISCV_ISA_EXT_ZVE64X 77 #define RISCV_ISA_EXT_ZVE64F 78 #define RISCV_ISA_EXT_ZVE64D 79 +#define RISCV_ISA_EXT_ZICCLSM 80 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 2fb8a8185e7a..023b7771d1b7 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -65,6 +65,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZVE64X (1ULL << 39) #define RISCV_HWPROBE_EXT_ZVE64F (1ULL << 40) #define RISCV_HWPROBE_EXT_ZVE64D (1ULL << 41) +#define RISCV_HWPROBE_EXT_ZICCLSM (1ULL << 42) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1d6e4fda00f8..83c5ae16ad5e 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -283,6 +283,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h), __RISCV_ISA_EXT_SUPERSET(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts), __RISCV_ISA_EXT_SUPERSET(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts), + __RISCV_ISA_EXT_DATA(zicclsm, RISCV_ISA_EXT_ZICCLSM), __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index e4ec9166339f..e910e2971984 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -96,6 +96,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZBB); EXT_KEY(ZBS); EXT_KEY(ZICBOZ); + EXT_KEY(ZICCLSM); EXT_KEY(ZBC); EXT_KEY(ZBKB);