| Message ID | 20240625165121.2160354-3-evan@rivosinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | RISC-V: hwprobe: Misaligned scalar perf fix and rename | expand |
On Tue, Jun 25, 2024 at 09:51:21AM -0700, Evan Green wrote: > In preparation for misaligned vector performance hwprobe keys, rename > the hwprobe key values associated with misaligned scalar accesses to > include the term SCALAR. > > Signed-off-by: Evan Green <evan@rivosinc.com> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> > > --- > > Changes in v2: > - Added patch to rename misaligned perf key values (Palmer) > > Documentation/arch/riscv/hwprobe.rst | 20 ++++++++++---------- > arch/riscv/include/uapi/asm/hwprobe.h | 10 +++++----- > arch/riscv/kernel/sys_hwprobe.c | 10 +++++----- > arch/riscv/kernel/traps_misaligned.c | 6 +++--- > arch/riscv/kernel/unaligned_access_speed.c | 12 ++++++------ > 5 files changed, 29 insertions(+), 29 deletions(-) > > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst > index c9f570b1ab60..83f7f3c1347f 100644 > --- a/Documentation/arch/riscv/hwprobe.rst > +++ b/Documentation/arch/riscv/hwprobe.rst > @@ -215,22 +215,22 @@ The following keys are defined: > the performance of misaligned scalar word accesses on the selected set of > processors. > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNKNOWN`: The performance of misaligned > - accesses is unknown. > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`: The performance of > + misaligned accesses is unknown. > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_EMULATED`: Misaligned accesses are > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`: Misaligned accesses are > emulated via software, either in or below the kernel. These accesses are > always extremely slow. > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_SLOW`: Misaligned word accesses are > - slower than equivalent byte accesses. Misaligned accesses may be supported > - directly in hardware, or trapped and emulated by software. > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`: Misaligned word accesses > + are slower than equivalent byte accesses. Misaligned accesses may be > + supported directly in hardware, or trapped and emulated by software. > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_FAST`: Misaligned word accesses are > - faster than equivalent byte accesses. > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`: Misaligned word accesses > + are faster than equivalent byte accesses. > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are > - not supported at all and will generate a misaligned address fault. > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`: Misaligned accesses > + are not supported at all and will generate a misaligned address fault. > > * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which > represents the size of the Zicboz block in bytes. > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > index 22073533cea8..e11684d8ae1c 100644 > --- a/arch/riscv/include/uapi/asm/hwprobe.h > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > @@ -66,11 +66,11 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_EXT_ZVE64F (1ULL << 40) > #define RISCV_HWPROBE_EXT_ZVE64D (1ULL << 41) > #define RISCV_HWPROBE_KEY_CPUPERF_0 5 > -#define RISCV_HWPROBE_MISALIGNED_UNKNOWN 0 > -#define RISCV_HWPROBE_MISALIGNED_EMULATED 1 > -#define RISCV_HWPROBE_MISALIGNED_SLOW 2 > -#define RISCV_HWPROBE_MISALIGNED_FAST 3 > -#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED 4 > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN 0 > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED 1 > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW 2 > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_FAST 3 > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED 4 > #define RISCV_HWPROBE_MISALIGNED_MASK 7 > #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6 > #define RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF 7 > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c > index 991ceba67717..fbf952e7383e 100644 > --- a/arch/riscv/kernel/sys_hwprobe.c > +++ b/arch/riscv/kernel/sys_hwprobe.c > @@ -170,13 +170,13 @@ static u64 hwprobe_misaligned(const struct cpumask *cpus) > perf = this_perf; > > if (perf != this_perf) { > - perf = RISCV_HWPROBE_MISALIGNED_UNKNOWN; > + perf = RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN; > break; > } > } > > if (perf == -1ULL) > - return RISCV_HWPROBE_MISALIGNED_UNKNOWN; > + return RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN; > > return perf; > } > @@ -184,12 +184,12 @@ static u64 hwprobe_misaligned(const struct cpumask *cpus) > static u64 hwprobe_misaligned(const struct cpumask *cpus) > { > if (IS_ENABLED(CONFIG_RISCV_EFFICIENT_UNALIGNED_ACCESS)) > - return RISCV_HWPROBE_MISALIGNED_FAST; > + return RISCV_HWPROBE_MISALIGNED_SCALAR_FAST; > > if (IS_ENABLED(CONFIG_RISCV_EMULATED_UNALIGNED_ACCESS) && unaligned_ctl_available()) > - return RISCV_HWPROBE_MISALIGNED_EMULATED; > + return RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED; > > - return RISCV_HWPROBE_MISALIGNED_SLOW; > + return RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW; > } > #endif > > diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c > index b62d5a2f4541..192cd5603e95 100644 > --- a/arch/riscv/kernel/traps_misaligned.c > +++ b/arch/riscv/kernel/traps_misaligned.c > @@ -338,7 +338,7 @@ int handle_misaligned_load(struct pt_regs *regs) > perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); > > #ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS > - *this_cpu_ptr(&misaligned_access_speed) = RISCV_HWPROBE_MISALIGNED_EMULATED; > + *this_cpu_ptr(&misaligned_access_speed) = RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED; > #endif > > if (!unaligned_enabled) > @@ -532,13 +532,13 @@ static bool check_unaligned_access_emulated(int cpu) > unsigned long tmp_var, tmp_val; > bool misaligned_emu_detected; > > - *mas_ptr = RISCV_HWPROBE_MISALIGNED_UNKNOWN; > + *mas_ptr = RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN; > > __asm__ __volatile__ ( > " "REG_L" %[tmp], 1(%[ptr])\n" > : [tmp] "=r" (tmp_val) : [ptr] "r" (&tmp_var) : "memory"); > > - misaligned_emu_detected = (*mas_ptr == RISCV_HWPROBE_MISALIGNED_EMULATED); > + misaligned_emu_detected = (*mas_ptr == RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED); > /* > * If unaligned_ctl is already set, this means that we detected that all > * CPUS uses emulated misaligned access at boot time. If that changed > diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c > index a9a6bcb02acf..160628a2116d 100644 > --- a/arch/riscv/kernel/unaligned_access_speed.c > +++ b/arch/riscv/kernel/unaligned_access_speed.c > @@ -34,9 +34,9 @@ static int check_unaligned_access(void *param) > struct page *page = param; > void *dst; > void *src; > - long speed = RISCV_HWPROBE_MISALIGNED_SLOW; > + long speed = RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW; > > - if (per_cpu(misaligned_access_speed, cpu) != RISCV_HWPROBE_MISALIGNED_UNKNOWN) > + if (per_cpu(misaligned_access_speed, cpu) != RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN) > return 0; > > /* Make an unaligned destination buffer. */ > @@ -95,14 +95,14 @@ static int check_unaligned_access(void *param) > } > > if (word_cycles < byte_cycles) > - speed = RISCV_HWPROBE_MISALIGNED_FAST; > + speed = RISCV_HWPROBE_MISALIGNED_SCALAR_FAST; > > ratio = div_u64((byte_cycles * 100), word_cycles); > pr_info("cpu%d: Ratio of byte access time to unaligned word access is %d.%02d, unaligned accesses are %s\n", > cpu, > ratio / 100, > ratio % 100, > - (speed == RISCV_HWPROBE_MISALIGNED_FAST) ? "fast" : "slow"); > + (speed == RISCV_HWPROBE_MISALIGNED_SCALAR_FAST) ? "fast" : "slow"); > > per_cpu(misaligned_access_speed, cpu) = speed; > > @@ -110,7 +110,7 @@ static int check_unaligned_access(void *param) > * Set the value of fast_misaligned_access of a CPU. These operations > * are atomic to avoid race conditions. > */ > - if (speed == RISCV_HWPROBE_MISALIGNED_FAST) > + if (speed == RISCV_HWPROBE_MISALIGNED_SCALAR_FAST) > cpumask_set_cpu(cpu, &fast_misaligned_access); > else > cpumask_clear_cpu(cpu, &fast_misaligned_access); > @@ -188,7 +188,7 @@ static int riscv_online_cpu(unsigned int cpu) > static struct page *buf; > > /* We are already set since the last check */ > - if (per_cpu(misaligned_access_speed, cpu) != RISCV_HWPROBE_MISALIGNED_UNKNOWN) > + if (per_cpu(misaligned_access_speed, cpu) != RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN) > goto exit; > > buf = alloc_pages(GFP_KERNEL, MISALIGNED_BUFFER_ORDER); > -- > 2.34.1 >
On Tue, Jun 25, 2024 at 09:51:21AM -0700, Evan Green wrote: > In preparation for misaligned vector performance hwprobe keys, rename > the hwprobe key values associated with misaligned scalar accesses to > include the term SCALAR. > > Signed-off-by: Evan Green <evan@rivosinc.com> > > --- > > Changes in v2: > - Added patch to rename misaligned perf key values (Palmer) > > Documentation/arch/riscv/hwprobe.rst | 20 ++++++++++---------- > arch/riscv/include/uapi/asm/hwprobe.h | 10 +++++----- > arch/riscv/kernel/sys_hwprobe.c | 10 +++++----- > arch/riscv/kernel/traps_misaligned.c | 6 +++--- > arch/riscv/kernel/unaligned_access_speed.c | 12 ++++++------ > 5 files changed, 29 insertions(+), 29 deletions(-) > > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst > index c9f570b1ab60..83f7f3c1347f 100644 > --- a/Documentation/arch/riscv/hwprobe.rst > +++ b/Documentation/arch/riscv/hwprobe.rst > @@ -215,22 +215,22 @@ The following keys are defined: > the performance of misaligned scalar word accesses on the selected set of > processors. > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNKNOWN`: The performance of misaligned > - accesses is unknown. > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`: The performance of > + misaligned accesses is unknown. > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_EMULATED`: Misaligned accesses are > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`: Misaligned accesses are > emulated via software, either in or below the kernel. These accesses are > always extremely slow. > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_SLOW`: Misaligned word accesses are > - slower than equivalent byte accesses. Misaligned accesses may be supported > - directly in hardware, or trapped and emulated by software. > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`: Misaligned word accesses > + are slower than equivalent byte accesses. Misaligned accesses may be > + supported directly in hardware, or trapped and emulated by software. > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_FAST`: Misaligned word accesses are > - faster than equivalent byte accesses. > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`: Misaligned word accesses > + are faster than equivalent byte accesses. > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are > - not supported at all and will generate a misaligned address fault. > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`: Misaligned accesses > + are not supported at all and will generate a misaligned address fault. > > * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which > represents the size of the Zicboz block in bytes. > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > index 22073533cea8..e11684d8ae1c 100644 > --- a/arch/riscv/include/uapi/asm/hwprobe.h > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > @@ -66,11 +66,11 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_EXT_ZVE64F (1ULL << 40) > #define RISCV_HWPROBE_EXT_ZVE64D (1ULL << 41) > #define RISCV_HWPROBE_KEY_CPUPERF_0 5 > -#define RISCV_HWPROBE_MISALIGNED_UNKNOWN 0 > -#define RISCV_HWPROBE_MISALIGNED_EMULATED 1 > -#define RISCV_HWPROBE_MISALIGNED_SLOW 2 > -#define RISCV_HWPROBE_MISALIGNED_FAST 3 > -#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED 4 > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN 0 > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED 1 > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW 2 > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_FAST 3 > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED 4 > #define RISCV_HWPROBE_MISALIGNED_MASK 7 How come the "old" names do not need to be preserved for userspace?
On Tue, Jun 25, 2024 at 11:35 AM Conor Dooley <conor@kernel.org> wrote: > > On Tue, Jun 25, 2024 at 09:51:21AM -0700, Evan Green wrote: > > In preparation for misaligned vector performance hwprobe keys, rename > > the hwprobe key values associated with misaligned scalar accesses to > > include the term SCALAR. > > > > Signed-off-by: Evan Green <evan@rivosinc.com> > > > > --- > > > > Changes in v2: > > - Added patch to rename misaligned perf key values (Palmer) > > > > Documentation/arch/riscv/hwprobe.rst | 20 ++++++++++---------- > > arch/riscv/include/uapi/asm/hwprobe.h | 10 +++++----- > > arch/riscv/kernel/sys_hwprobe.c | 10 +++++----- > > arch/riscv/kernel/traps_misaligned.c | 6 +++--- > > arch/riscv/kernel/unaligned_access_speed.c | 12 ++++++------ > > 5 files changed, 29 insertions(+), 29 deletions(-) > > > > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst > > index c9f570b1ab60..83f7f3c1347f 100644 > > --- a/Documentation/arch/riscv/hwprobe.rst > > +++ b/Documentation/arch/riscv/hwprobe.rst > > @@ -215,22 +215,22 @@ The following keys are defined: > > the performance of misaligned scalar word accesses on the selected set of > > processors. > > > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNKNOWN`: The performance of misaligned > > - accesses is unknown. > > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`: The performance of > > + misaligned accesses is unknown. > > > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_EMULATED`: Misaligned accesses are > > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`: Misaligned accesses are > > emulated via software, either in or below the kernel. These accesses are > > always extremely slow. > > > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_SLOW`: Misaligned word accesses are > > - slower than equivalent byte accesses. Misaligned accesses may be supported > > - directly in hardware, or trapped and emulated by software. > > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`: Misaligned word accesses > > + are slower than equivalent byte accesses. Misaligned accesses may be > > + supported directly in hardware, or trapped and emulated by software. > > > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_FAST`: Misaligned word accesses are > > - faster than equivalent byte accesses. > > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`: Misaligned word accesses > > + are faster than equivalent byte accesses. > > > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are > > - not supported at all and will generate a misaligned address fault. > > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`: Misaligned accesses > > + are not supported at all and will generate a misaligned address fault. > > > > * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which > > represents the size of the Zicboz block in bytes. > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > > index 22073533cea8..e11684d8ae1c 100644 > > --- a/arch/riscv/include/uapi/asm/hwprobe.h > > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > > @@ -66,11 +66,11 @@ struct riscv_hwprobe { > > #define RISCV_HWPROBE_EXT_ZVE64F (1ULL << 40) > > #define RISCV_HWPROBE_EXT_ZVE64D (1ULL << 41) > > #define RISCV_HWPROBE_KEY_CPUPERF_0 5 > > -#define RISCV_HWPROBE_MISALIGNED_UNKNOWN 0 > > -#define RISCV_HWPROBE_MISALIGNED_EMULATED 1 > > -#define RISCV_HWPROBE_MISALIGNED_SLOW 2 > > -#define RISCV_HWPROBE_MISALIGNED_FAST 3 > > -#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED 4 > > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN 0 > > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED 1 > > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW 2 > > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_FAST 3 > > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED 4 > > #define RISCV_HWPROBE_MISALIGNED_MASK 7 > > How come the "old" names do not need to be preserved for userspace? It depends on what exactly the big userspace compatibility rule is. This preserves binary compatibility, which I think is the big one, but breaks source compatibility, though with an easy translation to fix. We could keep the old names around, but then it seems sort of silly to introduce the new names. I introduced this patch upon request, so I don't personally have a horse in the race on this one. -Evan
On Tue, Jun 25, 2024 at 12:08:09PM -0700, Evan Green wrote: > On Tue, Jun 25, 2024 at 11:35 AM Conor Dooley <conor@kernel.org> wrote: > > > > On Tue, Jun 25, 2024 at 09:51:21AM -0700, Evan Green wrote: > > > In preparation for misaligned vector performance hwprobe keys, rename > > > the hwprobe key values associated with misaligned scalar accesses to > > > include the term SCALAR. > > > > > > Signed-off-by: Evan Green <evan@rivosinc.com> > > > > > > --- > > > > > > Changes in v2: > > > - Added patch to rename misaligned perf key values (Palmer) > > > > > > Documentation/arch/riscv/hwprobe.rst | 20 ++++++++++---------- > > > arch/riscv/include/uapi/asm/hwprobe.h | 10 +++++----- > > > arch/riscv/kernel/sys_hwprobe.c | 10 +++++----- > > > arch/riscv/kernel/traps_misaligned.c | 6 +++--- > > > arch/riscv/kernel/unaligned_access_speed.c | 12 ++++++------ > > > 5 files changed, 29 insertions(+), 29 deletions(-) > > > > > > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst > > > index c9f570b1ab60..83f7f3c1347f 100644 > > > --- a/Documentation/arch/riscv/hwprobe.rst > > > +++ b/Documentation/arch/riscv/hwprobe.rst > > > @@ -215,22 +215,22 @@ The following keys are defined: > > > the performance of misaligned scalar word accesses on the selected set of > > > processors. > > > > > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNKNOWN`: The performance of misaligned > > > - accesses is unknown. > > > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`: The performance of > > > + misaligned accesses is unknown. > > > > > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_EMULATED`: Misaligned accesses are > > > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`: Misaligned accesses are > > > emulated via software, either in or below the kernel. These accesses are > > > always extremely slow. > > > > > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_SLOW`: Misaligned word accesses are > > > - slower than equivalent byte accesses. Misaligned accesses may be supported > > > - directly in hardware, or trapped and emulated by software. > > > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`: Misaligned word accesses > > > + are slower than equivalent byte accesses. Misaligned accesses may be > > > + supported directly in hardware, or trapped and emulated by software. > > > > > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_FAST`: Misaligned word accesses are > > > - faster than equivalent byte accesses. > > > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`: Misaligned word accesses > > > + are faster than equivalent byte accesses. > > > > > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are > > > - not supported at all and will generate a misaligned address fault. > > > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`: Misaligned accesses > > > + are not supported at all and will generate a misaligned address fault. > > > > > > * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which > > > represents the size of the Zicboz block in bytes. > > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > > > index 22073533cea8..e11684d8ae1c 100644 > > > --- a/arch/riscv/include/uapi/asm/hwprobe.h > > > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > > > @@ -66,11 +66,11 @@ struct riscv_hwprobe { > > > #define RISCV_HWPROBE_EXT_ZVE64F (1ULL << 40) > > > #define RISCV_HWPROBE_EXT_ZVE64D (1ULL << 41) > > > #define RISCV_HWPROBE_KEY_CPUPERF_0 5 > > > -#define RISCV_HWPROBE_MISALIGNED_UNKNOWN 0 > > > -#define RISCV_HWPROBE_MISALIGNED_EMULATED 1 > > > -#define RISCV_HWPROBE_MISALIGNED_SLOW 2 > > > -#define RISCV_HWPROBE_MISALIGNED_FAST 3 > > > -#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED 4 > > > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN 0 > > > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED 1 > > > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW 2 > > > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_FAST 3 > > > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED 4 > > > #define RISCV_HWPROBE_MISALIGNED_MASK 7 > > > > How come the "old" names do not need to be preserved for userspace? > > It depends on what exactly the big userspace compatibility rule is. > This preserves binary compatibility, which I think is the big one, but > breaks source compatibility, though with an easy translation to fix. > We could keep the old names around, but then it seems sort of silly to > introduce the new names. I introduced this patch upon request, so I > don't personally have a horse in the race on this one. So apparently this isn't quite Palmer actually wanted. In today's call he suggested that he'd send a new version himself, but also that what we should do define a new key for scalar /and/ new add new defines values that contain the word scalar, retaining the old defines. The values can of course be the same.
On Wed, Jun 26, 2024 at 7:34 AM Conor Dooley <conor@kernel.org> wrote: > > On Tue, Jun 25, 2024 at 12:08:09PM -0700, Evan Green wrote: > > On Tue, Jun 25, 2024 at 11:35 AM Conor Dooley <conor@kernel.org> wrote: > > > > > > On Tue, Jun 25, 2024 at 09:51:21AM -0700, Evan Green wrote: > > > > In preparation for misaligned vector performance hwprobe keys, rename > > > > the hwprobe key values associated with misaligned scalar accesses to > > > > include the term SCALAR. > > > > > > > > Signed-off-by: Evan Green <evan@rivosinc.com> > > > > > > > > --- > > > > > > > > Changes in v2: > > > > - Added patch to rename misaligned perf key values (Palmer) > > > > > > > > Documentation/arch/riscv/hwprobe.rst | 20 ++++++++++---------- > > > > arch/riscv/include/uapi/asm/hwprobe.h | 10 +++++----- > > > > arch/riscv/kernel/sys_hwprobe.c | 10 +++++----- > > > > arch/riscv/kernel/traps_misaligned.c | 6 +++--- > > > > arch/riscv/kernel/unaligned_access_speed.c | 12 ++++++------ > > > > 5 files changed, 29 insertions(+), 29 deletions(-) > > > > > > > > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst > > > > index c9f570b1ab60..83f7f3c1347f 100644 > > > > --- a/Documentation/arch/riscv/hwprobe.rst > > > > +++ b/Documentation/arch/riscv/hwprobe.rst > > > > @@ -215,22 +215,22 @@ The following keys are defined: > > > > the performance of misaligned scalar word accesses on the selected set of > > > > processors. > > > > > > > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNKNOWN`: The performance of misaligned > > > > - accesses is unknown. > > > > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`: The performance of > > > > + misaligned accesses is unknown. > > > > > > > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_EMULATED`: Misaligned accesses are > > > > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`: Misaligned accesses are > > > > emulated via software, either in or below the kernel. These accesses are > > > > always extremely slow. > > > > > > > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_SLOW`: Misaligned word accesses are > > > > - slower than equivalent byte accesses. Misaligned accesses may be supported > > > > - directly in hardware, or trapped and emulated by software. > > > > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`: Misaligned word accesses > > > > + are slower than equivalent byte accesses. Misaligned accesses may be > > > > + supported directly in hardware, or trapped and emulated by software. > > > > > > > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_FAST`: Misaligned word accesses are > > > > - faster than equivalent byte accesses. > > > > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`: Misaligned word accesses > > > > + are faster than equivalent byte accesses. > > > > > > > > - * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are > > > > - not supported at all and will generate a misaligned address fault. > > > > + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`: Misaligned accesses > > > > + are not supported at all and will generate a misaligned address fault. > > > > > > > > * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which > > > > represents the size of the Zicboz block in bytes. > > > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > > > > index 22073533cea8..e11684d8ae1c 100644 > > > > --- a/arch/riscv/include/uapi/asm/hwprobe.h > > > > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > > > > @@ -66,11 +66,11 @@ struct riscv_hwprobe { > > > > #define RISCV_HWPROBE_EXT_ZVE64F (1ULL << 40) > > > > #define RISCV_HWPROBE_EXT_ZVE64D (1ULL << 41) > > > > #define RISCV_HWPROBE_KEY_CPUPERF_0 5 > > > > -#define RISCV_HWPROBE_MISALIGNED_UNKNOWN 0 > > > > -#define RISCV_HWPROBE_MISALIGNED_EMULATED 1 > > > > -#define RISCV_HWPROBE_MISALIGNED_SLOW 2 > > > > -#define RISCV_HWPROBE_MISALIGNED_FAST 3 > > > > -#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED 4 > > > > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN 0 > > > > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED 1 > > > > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW 2 > > > > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_FAST 3 > > > > +#define RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED 4 > > > > #define RISCV_HWPROBE_MISALIGNED_MASK 7 > > > > > > How come the "old" names do not need to be preserved for userspace? > > > > It depends on what exactly the big userspace compatibility rule is. > > This preserves binary compatibility, which I think is the big one, but > > breaks source compatibility, though with an easy translation to fix. > > We could keep the old names around, but then it seems sort of silly to > > introduce the new names. I introduced this patch upon request, so I > > don't personally have a horse in the race on this one. > > So apparently this isn't quite Palmer actually wanted. In today's call > he suggested that he'd send a new version himself, but also that what we > should do define a new key for scalar /and/ new add new defines values that > contain the word scalar, retaining the old defines. The values can of > course be the same. Ahh, got it. I'm happy to spin this. -Evan
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index c9f570b1ab60..83f7f3c1347f 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -215,22 +215,22 @@ The following keys are defined: the performance of misaligned scalar word accesses on the selected set of processors. - * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNKNOWN`: The performance of misaligned - accesses is unknown. + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN`: The performance of + misaligned accesses is unknown. - * :c:macro:`RISCV_HWPROBE_MISALIGNED_EMULATED`: Misaligned accesses are + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED`: Misaligned accesses are emulated via software, either in or below the kernel. These accesses are always extremely slow. - * :c:macro:`RISCV_HWPROBE_MISALIGNED_SLOW`: Misaligned word accesses are - slower than equivalent byte accesses. Misaligned accesses may be supported - directly in hardware, or trapped and emulated by software. + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW`: Misaligned word accesses + are slower than equivalent byte accesses. Misaligned accesses may be + supported directly in hardware, or trapped and emulated by software. - * :c:macro:`RISCV_HWPROBE_MISALIGNED_FAST`: Misaligned word accesses are - faster than equivalent byte accesses. + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_FAST`: Misaligned word accesses + are faster than equivalent byte accesses. - * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are - not supported at all and will generate a misaligned address fault. + * :c:macro:`RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED`: Misaligned accesses + are not supported at all and will generate a misaligned address fault. * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which represents the size of the Zicboz block in bytes. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 22073533cea8..e11684d8ae1c 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -66,11 +66,11 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZVE64F (1ULL << 40) #define RISCV_HWPROBE_EXT_ZVE64D (1ULL << 41) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 -#define RISCV_HWPROBE_MISALIGNED_UNKNOWN 0 -#define RISCV_HWPROBE_MISALIGNED_EMULATED 1 -#define RISCV_HWPROBE_MISALIGNED_SLOW 2 -#define RISCV_HWPROBE_MISALIGNED_FAST 3 -#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED 4 +#define RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN 0 +#define RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED 1 +#define RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW 2 +#define RISCV_HWPROBE_MISALIGNED_SCALAR_FAST 3 +#define RISCV_HWPROBE_MISALIGNED_SCALAR_UNSUPPORTED 4 #define RISCV_HWPROBE_MISALIGNED_MASK 7 #define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6 #define RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF 7 diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index 991ceba67717..fbf952e7383e 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -170,13 +170,13 @@ static u64 hwprobe_misaligned(const struct cpumask *cpus) perf = this_perf; if (perf != this_perf) { - perf = RISCV_HWPROBE_MISALIGNED_UNKNOWN; + perf = RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN; break; } } if (perf == -1ULL) - return RISCV_HWPROBE_MISALIGNED_UNKNOWN; + return RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN; return perf; } @@ -184,12 +184,12 @@ static u64 hwprobe_misaligned(const struct cpumask *cpus) static u64 hwprobe_misaligned(const struct cpumask *cpus) { if (IS_ENABLED(CONFIG_RISCV_EFFICIENT_UNALIGNED_ACCESS)) - return RISCV_HWPROBE_MISALIGNED_FAST; + return RISCV_HWPROBE_MISALIGNED_SCALAR_FAST; if (IS_ENABLED(CONFIG_RISCV_EMULATED_UNALIGNED_ACCESS) && unaligned_ctl_available()) - return RISCV_HWPROBE_MISALIGNED_EMULATED; + return RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED; - return RISCV_HWPROBE_MISALIGNED_SLOW; + return RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW; } #endif diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index b62d5a2f4541..192cd5603e95 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -338,7 +338,7 @@ int handle_misaligned_load(struct pt_regs *regs) perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); #ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS - *this_cpu_ptr(&misaligned_access_speed) = RISCV_HWPROBE_MISALIGNED_EMULATED; + *this_cpu_ptr(&misaligned_access_speed) = RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED; #endif if (!unaligned_enabled) @@ -532,13 +532,13 @@ static bool check_unaligned_access_emulated(int cpu) unsigned long tmp_var, tmp_val; bool misaligned_emu_detected; - *mas_ptr = RISCV_HWPROBE_MISALIGNED_UNKNOWN; + *mas_ptr = RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN; __asm__ __volatile__ ( " "REG_L" %[tmp], 1(%[ptr])\n" : [tmp] "=r" (tmp_val) : [ptr] "r" (&tmp_var) : "memory"); - misaligned_emu_detected = (*mas_ptr == RISCV_HWPROBE_MISALIGNED_EMULATED); + misaligned_emu_detected = (*mas_ptr == RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED); /* * If unaligned_ctl is already set, this means that we detected that all * CPUS uses emulated misaligned access at boot time. If that changed diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c index a9a6bcb02acf..160628a2116d 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -34,9 +34,9 @@ static int check_unaligned_access(void *param) struct page *page = param; void *dst; void *src; - long speed = RISCV_HWPROBE_MISALIGNED_SLOW; + long speed = RISCV_HWPROBE_MISALIGNED_SCALAR_SLOW; - if (per_cpu(misaligned_access_speed, cpu) != RISCV_HWPROBE_MISALIGNED_UNKNOWN) + if (per_cpu(misaligned_access_speed, cpu) != RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN) return 0; /* Make an unaligned destination buffer. */ @@ -95,14 +95,14 @@ static int check_unaligned_access(void *param) } if (word_cycles < byte_cycles) - speed = RISCV_HWPROBE_MISALIGNED_FAST; + speed = RISCV_HWPROBE_MISALIGNED_SCALAR_FAST; ratio = div_u64((byte_cycles * 100), word_cycles); pr_info("cpu%d: Ratio of byte access time to unaligned word access is %d.%02d, unaligned accesses are %s\n", cpu, ratio / 100, ratio % 100, - (speed == RISCV_HWPROBE_MISALIGNED_FAST) ? "fast" : "slow"); + (speed == RISCV_HWPROBE_MISALIGNED_SCALAR_FAST) ? "fast" : "slow"); per_cpu(misaligned_access_speed, cpu) = speed; @@ -110,7 +110,7 @@ static int check_unaligned_access(void *param) * Set the value of fast_misaligned_access of a CPU. These operations * are atomic to avoid race conditions. */ - if (speed == RISCV_HWPROBE_MISALIGNED_FAST) + if (speed == RISCV_HWPROBE_MISALIGNED_SCALAR_FAST) cpumask_set_cpu(cpu, &fast_misaligned_access); else cpumask_clear_cpu(cpu, &fast_misaligned_access); @@ -188,7 +188,7 @@ static int riscv_online_cpu(unsigned int cpu) static struct page *buf; /* We are already set since the last check */ - if (per_cpu(misaligned_access_speed, cpu) != RISCV_HWPROBE_MISALIGNED_UNKNOWN) + if (per_cpu(misaligned_access_speed, cpu) != RISCV_HWPROBE_MISALIGNED_SCALAR_UNKNOWN) goto exit; buf = alloc_pages(GFP_KERNEL, MISALIGNED_BUFFER_ORDER);
In preparation for misaligned vector performance hwprobe keys, rename the hwprobe key values associated with misaligned scalar accesses to include the term SCALAR. Signed-off-by: Evan Green <evan@rivosinc.com> --- Changes in v2: - Added patch to rename misaligned perf key values (Palmer) Documentation/arch/riscv/hwprobe.rst | 20 ++++++++++---------- arch/riscv/include/uapi/asm/hwprobe.h | 10 +++++----- arch/riscv/kernel/sys_hwprobe.c | 10 +++++----- arch/riscv/kernel/traps_misaligned.c | 6 +++--- arch/riscv/kernel/unaligned_access_speed.c | 12 ++++++------ 5 files changed, 29 insertions(+), 29 deletions(-)