| Message ID | 20240718004808.2246354-2-samuel.holland@sifive.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | riscv: Per-thread envcfg CSR support | expand |
On Wed, Jul 17, 2024 at 05:47:54PM -0700, Samuel Holland wrote: > Currently, we enable cbo.zero for usermode on each hart that supports > the Zicboz extension. This means that the [ms]envcfg CSR value may > differ between harts. Other features, such as pointer masking and CFI, > require setting [ms]envcfg bits on a per-thread basis. The combination > of these two adds quite some complexity and overhead to context > switching, as we would need to maintain two separate masks for the > per-hart and per-thread bits. Andrew Jones, who originally added Zicboz > support, writes[1][2]: > > I've approached Zicboz the same way I would approach all > extensions, which is to be per-hart. I'm not currently aware of > a platform that is / will be composed of harts where some have > Zicboz and others don't, but there's nothing stopping a platform > like that from being built. > > So, how about we add code that confirms Zicboz is on all harts. > If any hart does not have it, then we complain loudly and disable > it on all the other harts. If it was just a hardware description > bug, then it'll get fixed. If there's actually a platform which > doesn't have Zicboz on all harts, then, when the issue is reported, > we can decide to not support it, support it with defconfig, or > support it under a Kconfig guard which must be enabled by the user. > > Let's follow his suggested solution and require the extension to be > available on all harts, so the envcfg CSR value does not need to change > when a thread migrates between harts. Since we are doing this for all > extensions with fields in envcfg, the CSR itself only needs to be saved/ > restored when it is present on all harts. > > This should not be a regression as no known hardware has asymmetric > Zicboz support, but if anyone reports seeing the warning, we will > re-evaluate our solution. > > Link: https://lore.kernel.org/linux-riscv/20240322-168f191eeb8479b2ea169a5e@orel/ [1] > Link: https://lore.kernel.org/linux-riscv/20240323-28943722feb57a41fb0ff488@orel/ [2] > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> > Reviewed-by: Deepak Gupta <debug@rivosinc.com> > Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Charlie Jenkins <charlie@rivosinc.com> > --- > > Changes in v3: > - Rebase on riscv/for-next > > arch/riscv/kernel/cpufeature.c | 7 ++++++- > arch/riscv/kernel/suspend.c | 4 ++-- > 2 files changed, 8 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 0366dc3baf33..4efaf12b470e 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -27,6 +27,8 @@ > > #define NUM_ALPHA_EXTS ('z' - 'a' + 1) > > +static bool any_cpu_has_zicboz; > + > unsigned long elf_hwcap __read_mostly; > > /* Host ISA bitmap */ > @@ -97,6 +99,7 @@ static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data, > pr_err("Zicboz disabled as cboz-block-size present, but is not a power-of-2\n"); > return -EINVAL; > } > + any_cpu_has_zicboz = true; > return 0; > } > > @@ -874,8 +877,10 @@ unsigned long riscv_get_elf_hwcap(void) > > void riscv_user_isa_enable(void) > { > - if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ)) > + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOZ)) > csr_set(CSR_ENVCFG, ENVCFG_CBZE); > + else if (any_cpu_has_zicboz) > + pr_warn_once("Zicboz disabled as it is unavailable on some harts\n"); > } > > #ifdef CONFIG_RISCV_ALTERNATIVE > diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c > index c8cec0cc5833..9a8a0dc035b2 100644 > --- a/arch/riscv/kernel/suspend.c > +++ b/arch/riscv/kernel/suspend.c > @@ -14,7 +14,7 @@ > > void suspend_save_csrs(struct suspend_context *context) > { > - if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG)) > + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_XLINUXENVCFG)) > context->envcfg = csr_read(CSR_ENVCFG); > context->tvec = csr_read(CSR_TVEC); > context->ie = csr_read(CSR_IE); > @@ -37,7 +37,7 @@ void suspend_save_csrs(struct suspend_context *context) > void suspend_restore_csrs(struct suspend_context *context) > { > csr_write(CSR_SCRATCH, 0); > - if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG)) > + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_XLINUXENVCFG)) > csr_write(CSR_ENVCFG, context->envcfg); > csr_write(CSR_TVEC, context->tvec); > csr_write(CSR_IE, context->ie); > -- > 2.45.1 >
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 0366dc3baf33..4efaf12b470e 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -27,6 +27,8 @@ #define NUM_ALPHA_EXTS ('z' - 'a' + 1) +static bool any_cpu_has_zicboz; + unsigned long elf_hwcap __read_mostly; /* Host ISA bitmap */ @@ -97,6 +99,7 @@ static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data, pr_err("Zicboz disabled as cboz-block-size present, but is not a power-of-2\n"); return -EINVAL; } + any_cpu_has_zicboz = true; return 0; } @@ -874,8 +877,10 @@ unsigned long riscv_get_elf_hwcap(void) void riscv_user_isa_enable(void) { - if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ)) + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOZ)) csr_set(CSR_ENVCFG, ENVCFG_CBZE); + else if (any_cpu_has_zicboz) + pr_warn_once("Zicboz disabled as it is unavailable on some harts\n"); } #ifdef CONFIG_RISCV_ALTERNATIVE diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c index c8cec0cc5833..9a8a0dc035b2 100644 --- a/arch/riscv/kernel/suspend.c +++ b/arch/riscv/kernel/suspend.c @@ -14,7 +14,7 @@ void suspend_save_csrs(struct suspend_context *context) { - if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG)) + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_XLINUXENVCFG)) context->envcfg = csr_read(CSR_ENVCFG); context->tvec = csr_read(CSR_TVEC); context->ie = csr_read(CSR_IE); @@ -37,7 +37,7 @@ void suspend_save_csrs(struct suspend_context *context) void suspend_restore_csrs(struct suspend_context *context) { csr_write(CSR_SCRATCH, 0); - if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG)) + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_XLINUXENVCFG)) csr_write(CSR_ENVCFG, context->envcfg); csr_write(CSR_TVEC, context->tvec); csr_write(CSR_IE, context->ie);