| Message ID | 20240731072405.197046-5-alexghiti@rivosinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Zacas/Zabha support and qspinlocks | expand |
On Wed, Jul 31, 2024 at 09:23:56AM +0200, Alexandre Ghiti wrote: > Add description for the Zabha ISA extension which was ratified in April > 2024. > > Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> > Reviewed-by: Guo Ren <guoren@kernel.org> > --- > Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > index a06dbc6b4928..a63578b95c4a 100644 > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > @@ -171,6 +171,12 @@ properties: > memory types as ratified in the 20191213 version of the privileged > ISA specification. > > + - const: zabha > + description: | > + The Zabha extension for Byte and Halfword Atomic Memory Operations > + as ratified at commit 49f49c842ff9 ("Update to Rafified state") of > + riscv-zabha. Acked-by: Conor Dooley <conor.dooley@microchip.com>
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index a06dbc6b4928..a63578b95c4a 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -171,6 +171,12 @@ properties: memory types as ratified in the 20191213 version of the privileged ISA specification. + - const: zabha + description: | + The Zabha extension for Byte and Halfword Atomic Memory Operations + as ratified at commit 49f49c842ff9 ("Update to Rafified state") of + riscv-zabha. + - const: zacas description: | The Zacas extension for Atomic Compare-and-Swap (CAS) instructions