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([2a01:4262:1ab:c:bbf4:eba3:898f:7501]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a80f411bdcbsm182316866b.105.2024.08.14.07.56.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Aug 2024 07:56:46 -0700 (PDT) From: Emil Renner Berthing To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Anup Patel Cc: Thomas Gleixner , Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou Subject: [PATCH v1 3/9] Revert "irqchip/sifive-plic: Improve locking safety by using irqsave/irqrestore" Date: Wed, 14 Aug 2024 16:56:35 +0200 Message-ID: <20240814145642.344485-4-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240814145642.344485-1-emil.renner.berthing@canonical.com> References: <20240814145642.344485-1-emil.renner.berthing@canonical.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240814_075655_762779_6D45BEEF X-CRM114-Status: GOOD ( 12.69 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This reverts commit abb7205794900503d6358ef1fb645373753a794d. This is a prerequisite to reverting the patch converting the PLIC into a platform driver. Unfortunately this breaks booting the Allwinner D1 SoC. Fixes: 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platform driver") Signed-off-by: Emil Renner Berthing --- drivers/irqchip/irq-sifive-plic.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index f3d4cb9e34f7..cbccd1da3ea1 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -103,11 +103,9 @@ static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable) static void plic_toggle(struct plic_handler *handler, int hwirq, int enable) { - unsigned long flags; - - raw_spin_lock_irqsave(&handler->enable_lock, flags); + raw_spin_lock(&handler->enable_lock); __plic_toggle(handler->enable_base, hwirq, enable); - raw_spin_unlock_irqrestore(&handler->enable_lock, flags); + raw_spin_unlock(&handler->enable_lock); } static inline void plic_irq_toggle(const struct cpumask *mask, @@ -244,7 +242,6 @@ static int plic_irq_set_type(struct irq_data *d, unsigned int type) static int plic_irq_suspend(void) { unsigned int i, cpu; - unsigned long flags; u32 __iomem *reg; struct plic_priv *priv; @@ -262,12 +259,12 @@ static int plic_irq_suspend(void) if (!handler->present) continue; - raw_spin_lock_irqsave(&handler->enable_lock, flags); + raw_spin_lock(&handler->enable_lock); for (i = 0; i < DIV_ROUND_UP(priv->nr_irqs, 32); i++) { reg = handler->enable_base + i * sizeof(u32); handler->enable_save[i] = readl(reg); } - raw_spin_unlock_irqrestore(&handler->enable_lock, flags); + raw_spin_unlock(&handler->enable_lock); } return 0; @@ -276,7 +273,6 @@ static int plic_irq_suspend(void) static void plic_irq_resume(void) { unsigned int i, index, cpu; - unsigned long flags; u32 __iomem *reg; struct plic_priv *priv; @@ -294,12 +290,12 @@ static void plic_irq_resume(void) if (!handler->present) continue; - raw_spin_lock_irqsave(&handler->enable_lock, flags); + raw_spin_lock(&handler->enable_lock); for (i = 0; i < DIV_ROUND_UP(priv->nr_irqs, 32); i++) { reg = handler->enable_base + i * sizeof(u32); writel(handler->enable_save[i], reg); } - raw_spin_unlock_irqrestore(&handler->enable_lock, flags); + raw_spin_unlock(&handler->enable_lock); } }