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AJvYcCWpgmJ3m/k6zqOi+P9i7aMw0F/qzxb14s35pS7roMGfaUQ7MWxshtH1Y6rbJGF4QGwat4lkew4y9q5dfb5TQ2eLt4zO+Kevsslf2fc55u+j X-Gm-Message-State: AOJu0YzFZkN6jJG2zl3Cl9CYnBp2gFQ6HtBs+yxPWUQkCyJuoqgt+EoN 60i3oS0VYbGyRcZTO2vEttnNtnjrTyYVTIqBGWILiOanhmVclYJVbT1CIRKdf4g= X-Google-Smtp-Source: AGHT+IHC66VEYQdljRuTuSO2x/zOwIVJbZPl2UlJTONTu2DLilQDdVvPTmdGUvtQ7FJ0ndbu7er3LA== X-Received: by 2002:a05:6871:328c:b0:261:d43:3eeb with SMTP id 586e51a60fabf-26fe5c082a6mr5371911fac.32.1723683436253; Wed, 14 Aug 2024 17:57:16 -0700 (PDT) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7c6b63570a9sm164518a12.60.2024.08.14.17.57.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Aug 2024 17:57:15 -0700 (PDT) From: Samuel Holland To: Palmer Dabbelt Cc: Samuel Holland , stable@vger.kernel.org, Albert Ou , Ben Dooks , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Charlie Jenkins , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Conor Dooley , Evan Green , Paul Walmsley , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH] riscv: misaligned: Restrict user access to kernel memory Date: Wed, 14 Aug 2024 17:57:03 -0700 Message-ID: <20240815005714.1163136-1-samuel.holland@sifive.com> X-Mailer: git-send-email 2.45.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240814_175717_703928_3A0B84C2 X-CRM114-Status: GOOD ( 10.77 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org raw_copy_{to,from}_user() do not call access_ok(), so this code allowed userspace to access any virtual memory address. Cc: stable@vger.kernel.org Fixes: 7c83232161f6 ("riscv: add support for misaligned trap handling in S-mode") Fixes: 441381506ba7 ("riscv: misaligned: remove CONFIG_RISCV_M_MODE specific code") Signed-off-by: Samuel Holland Reviewed-by: Alexandre Ghiti --- arch/riscv/kernel/traps_misaligned.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index b62d5a2f4541..1a76f99ff185 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -417,7 +417,7 @@ int handle_misaligned_load(struct pt_regs *regs) val.data_u64 = 0; if (user_mode(regs)) { - if (raw_copy_from_user(&val, (u8 __user *)addr, len)) + if (copy_from_user(&val, (u8 __user *)addr, len)) return -1; } else { memcpy(&val, (u8 *)addr, len); @@ -515,7 +515,7 @@ int handle_misaligned_store(struct pt_regs *regs) return -EOPNOTSUPP; if (user_mode(regs)) { - if (raw_copy_to_user((u8 __user *)addr, &val, len)) + if (copy_to_user((u8 __user *)addr, &val, len)) return -1; } else { memcpy((u8 *)addr, &val, len);