| Message ID | 20240927-dev-maxh-svukte-rebase-2-v2-2-9afe57c33aee@sifive.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | riscv: add Svukte extension | expand |
On Fri, Sep 27, 2024 at 09:41:44PM +0800, Max Hsu wrote: >Svukte extension introduce senvcfg.UKTE, hstatus.HUKTE. > >This patch add CSR bit definition, and detects if Svukte ISA extension >is available, cpufeature will set the correspond bit field so the >svukte-qualified memory accesses are protected in a manner that is >timing-independent of the faulting virtual address. > >Since hstatus.HU is not enabled by linux, enabling hstatus.HUKTE will >not be affective. > >This patch depends on patch "riscv: Per-thread envcfg CSR support" [1] > >Link: https://lore.kernel.org/linux-riscv/20240814081126.956287-1-samuel.holland@sifive.com/ [1] > >Reviewed-by: Samuel Holland <samuel.holland@sifive.com> >Signed-off-by: Max Hsu <max.hsu@sifive.com> >--- > arch/riscv/include/asm/csr.h | 2 ++ > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/kernel/cpufeature.c | 4 ++++ > 3 files changed, 7 insertions(+) > >diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h >index 25966995da04e090ff22a11e35be9bc24712f1a8..62b50667d539c50a0bfdadd1c6ab06cda948f6a8 100644 >--- a/arch/riscv/include/asm/csr.h >+++ b/arch/riscv/include/asm/csr.h >@@ -122,6 +122,7 @@ > #define HSTATUS_VSXL _AC(0x300000000, UL) > #define HSTATUS_VSXL_SHIFT 32 > #endif >+#define HSTATUS_HUKTE _AC(0x01000000, UL) > #define HSTATUS_VTSR _AC(0x00400000, UL) > #define HSTATUS_VTW _AC(0x00200000, UL) > #define HSTATUS_VTVM _AC(0x00100000, UL) >@@ -195,6 +196,7 @@ > /* xENVCFG flags */ > #define ENVCFG_STCE (_AC(1, ULL) << 63) > #define ENVCFG_PBMTE (_AC(1, ULL) << 62) >+#define ENVCFG_UKTE (_AC(1, UL) << 8) > #define ENVCFG_CBZE (_AC(1, UL) << 7) > #define ENVCFG_CBCFE (_AC(1, UL) << 6) > #define ENVCFG_CBIE_SHIFT 4 >diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h >index 46d9de54179ed40aa7b1ea0ec011fd6eea7218df..3591a4f40131ff5958c07857a1bd1624723d6550 100644 >--- a/arch/riscv/include/asm/hwcap.h >+++ b/arch/riscv/include/asm/hwcap.h >@@ -93,6 +93,7 @@ > #define RISCV_ISA_EXT_ZCMOP 84 > #define RISCV_ISA_EXT_ZAWRS 85 > #define RISCV_ISA_EXT_SVVPTC 86 >+#define RISCV_ISA_EXT_SVUKTE 87 > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > >diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c >index 3a8eeaa9310c32fce2141aff534dc4432b32abbe..e0853cae1dc0ba844d5969a42c30d44287e3250a 100644 >--- a/arch/riscv/kernel/cpufeature.c >+++ b/arch/riscv/kernel/cpufeature.c >@@ -381,6 +381,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), > __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), > __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), >+ __RISCV_ISA_EXT_SUPERSET(svukte, RISCV_ISA_EXT_SVUKTE, riscv_xlinuxenvcfg_exts), > __RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC), > }; > >@@ -921,6 +922,9 @@ void riscv_user_isa_enable(void) > { > if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ)) > csr_set(CSR_ENVCFG, ENVCFG_CBZE); >+ >+ if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVUKTE)) >+ current->thread.envcfg |= ENVCFG_UKTE; Pending merge of samuel's patches, this looks good to me. Reviewed-by: Deepak Gupta <debug@rivosinc.com> > } > > #ifdef CONFIG_RISCV_ALTERNATIVE > >-- >2.43.2 > >
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 25966995da04e090ff22a11e35be9bc24712f1a8..62b50667d539c50a0bfdadd1c6ab06cda948f6a8 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -122,6 +122,7 @@ #define HSTATUS_VSXL _AC(0x300000000, UL) #define HSTATUS_VSXL_SHIFT 32 #endif +#define HSTATUS_HUKTE _AC(0x01000000, UL) #define HSTATUS_VTSR _AC(0x00400000, UL) #define HSTATUS_VTW _AC(0x00200000, UL) #define HSTATUS_VTVM _AC(0x00100000, UL) @@ -195,6 +196,7 @@ /* xENVCFG flags */ #define ENVCFG_STCE (_AC(1, ULL) << 63) #define ENVCFG_PBMTE (_AC(1, ULL) << 62) +#define ENVCFG_UKTE (_AC(1, UL) << 8) #define ENVCFG_CBZE (_AC(1, UL) << 7) #define ENVCFG_CBCFE (_AC(1, UL) << 6) #define ENVCFG_CBIE_SHIFT 4 diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 46d9de54179ed40aa7b1ea0ec011fd6eea7218df..3591a4f40131ff5958c07857a1bd1624723d6550 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -93,6 +93,7 @@ #define RISCV_ISA_EXT_ZCMOP 84 #define RISCV_ISA_EXT_ZAWRS 85 #define RISCV_ISA_EXT_SVVPTC 86 +#define RISCV_ISA_EXT_SVUKTE 87 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3a8eeaa9310c32fce2141aff534dc4432b32abbe..e0853cae1dc0ba844d5969a42c30d44287e3250a 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -381,6 +381,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), + __RISCV_ISA_EXT_SUPERSET(svukte, RISCV_ISA_EXT_SVUKTE, riscv_xlinuxenvcfg_exts), __RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC), }; @@ -921,6 +922,9 @@ void riscv_user_isa_enable(void) { if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ)) csr_set(CSR_ENVCFG, ENVCFG_CBZE); + + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SVUKTE)) + current->thread.envcfg |= ENVCFG_UKTE; } #ifdef CONFIG_RISCV_ALTERNATIVE