| Message ID | 20240930-th1520-pinctrl-v3-6-32cea2bdbecb@tenstorrent.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | pinctrl: Add T-Head TH1520 SoC pin controllers | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/vmtest-fixes-PR | fail | merge-conflict |
Drew Fustini wrote: > From: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > Add names for the GPIO00-GPIO14 lines of the SO-DIMM module. > > Tested-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com> > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > Signed-off-by: Drew Fustini <dfustini@tenstorrent.com> > --- > .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 39 ++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > index bf1c639072b8..ca84bc2039ef 100644 > --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi > @@ -29,6 +29,12 @@ &aonsys_clk { > clock-frequency = <73728000>; > }; > > +&aogpio { > + gpio-line-names = "", "", "", > + "GPIO00", > + "GPIO04"; > +}; > + > &dmac0 { > status = "okay"; > }; > @@ -48,3 +54,36 @@ &sdio0 { > max-frequency = <198000000>; > status = "okay"; > }; > + > +&gpio0 { > + gpio-line-names = "", "", "", "", "", "", "", "", "", "", > + "", "", "", "", "", "", "", "", "", "", > + "", "", "", "", > + "GPIO07", > + "GPIO08", > + "", > + "GPIO01", > + "GPIO02"; > +}; > + > +&gpio1 { > + gpio-line-names = "", "", "", > + "GPIO11", > + "GPIO12", > + "GPIO13", > + "GPIO14", > + "", "", "", "", "", "", "", "", "", "", > + "", "", "", "", "", > + "GPIO06"; > +}; > + > +&gpio2 { > + gpio-line-names = "GPIO03", > + "GPIO05"; > +}; > + > +&gpio3 { > + gpio-line-names = "", "", > + "GPIO09", > + "GPIO10"; > +}; Hi Drew, I just noticed you've moved these entries compared to my original patches, so they're no longer sorted alphabetically. Why? Please see https://docs.kernel.org/devicetree/bindings/dts-coding-style.html under "Order of Nodes". /Emil
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index bf1c639072b8..ca84bc2039ef 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -29,6 +29,12 @@ &aonsys_clk { clock-frequency = <73728000>; }; +&aogpio { + gpio-line-names = "", "", "", + "GPIO00", + "GPIO04"; +}; + &dmac0 { status = "okay"; }; @@ -48,3 +54,36 @@ &sdio0 { max-frequency = <198000000>; status = "okay"; }; + +&gpio0 { + gpio-line-names = "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", + "GPIO07", + "GPIO08", + "", + "GPIO01", + "GPIO02"; +}; + +&gpio1 { + gpio-line-names = "", "", "", + "GPIO11", + "GPIO12", + "GPIO13", + "GPIO14", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", + "GPIO06"; +}; + +&gpio2 { + gpio-line-names = "GPIO03", + "GPIO05"; +}; + +&gpio3 { + gpio-line-names = "", "", + "GPIO09", + "GPIO10"; +};