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AJvYcCUpKfPHOXaq4hlHZO4DqMZu1Qx8YPcOoss8TxzzYr2Gygt3b1EeWlbQA8QhWO8JxCI90UhtfaoVqQae+Q==@lists.infradead.org X-Gm-Message-State: AOJu0YxvI8/L2kc9/7AHwe4NlCK+1TS8OIkAdPlANiLUIcxVAW2DQjTN 0JxNfrsjTcxZ6125up/O4eakmbQ/ga7dbpZyDlHywFfEcXsgR7dRkDmw0AZtqJ0= X-Google-Smtp-Source: AGHT+IGIGEeeGnC+KScU7RsGDXnOT3F+tOuXMVMoo+fGP2CQIBFtA2wtlRRoG48p3wyuBbKw6oUq4g== X-Received: by 2002:a05:6a20:b40b:b0:1d9:b78:2dd3 with SMTP id adf61e73a8af0-1d92c5100b6mr19225561637.26.1729562370603; Mon, 21 Oct 2024 18:59:30 -0700 (PDT) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71ec132ffdcsm3600710b3a.46.2024.10.21.18.59.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Oct 2024 18:59:29 -0700 (PDT) From: Samuel Holland To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Andrey Ryabinin , Alexander Potapenko , Andrey Konovalov , Dmitry Vyukov , Vincenzo Frascino , kasan-dev@googlegroups.com Cc: llvm@lists.linux.dev, Catalin Marinas , linux-kernel@vger.kernel.org, linux-mm@kvack.org, Alexandre Ghiti , Will Deacon , Evgenii Stepanov , Andrew Morton , linux-arm-kernel@lists.infradead.org, =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Samuel Holland Subject: [PATCH v2 8/9] riscv: Add SBI Firmware Features extension definitions Date: Mon, 21 Oct 2024 18:57:16 -0700 Message-ID: <20241022015913.3524425-9-samuel.holland@sifive.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20241022015913.3524425-1-samuel.holland@sifive.com> References: <20241022015913.3524425-1-samuel.holland@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241021_185931_543126_B45FA779 X-CRM114-Status: GOOD ( 10.20 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Clément Léger Add necessary SBI definitions to use the FWFT extension. [Samuel: Add SBI_FWFT_POINTER_MASKING_PMLEN] Signed-off-by: Clément Léger Signed-off-by: Samuel Holland --- Changes in v2: - New patch for v2 arch/riscv/include/asm/sbi.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 98f631b051db..4a35c6ffe49f 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -34,6 +34,7 @@ enum sbi_ext_id { SBI_EXT_PMU = 0x504D55, SBI_EXT_DBCN = 0x4442434E, SBI_EXT_STA = 0x535441, + SBI_EXT_FWFT = 0x46574654, /* Experimentals extensions must lie within this range */ SBI_EXT_EXPERIMENTAL_START = 0x08000000, @@ -281,6 +282,33 @@ struct sbi_sta_struct { #define SBI_SHMEM_DISABLE -1 +/* SBI function IDs for FW feature extension */ +#define SBI_EXT_FWFT_SET 0x0 +#define SBI_EXT_FWFT_GET 0x1 + +enum sbi_fwft_feature_t { + SBI_FWFT_MISALIGNED_EXC_DELEG = 0x0, + SBI_FWFT_LANDING_PAD = 0x1, + SBI_FWFT_SHADOW_STACK = 0x2, + SBI_FWFT_DOUBLE_TRAP = 0x3, + SBI_FWFT_PTE_AD_HW_UPDATING = 0x4, + SBI_FWFT_POINTER_MASKING_PMLEN = 0x5, + SBI_FWFT_LOCAL_RESERVED_START = 0x6, + SBI_FWFT_LOCAL_RESERVED_END = 0x3fffffff, + SBI_FWFT_LOCAL_PLATFORM_START = 0x40000000, + SBI_FWFT_LOCAL_PLATFORM_END = 0x7fffffff, + + SBI_FWFT_GLOBAL_RESERVED_START = 0x80000000, + SBI_FWFT_GLOBAL_RESERVED_END = 0xbfffffff, + SBI_FWFT_GLOBAL_PLATFORM_START = 0xc0000000, + SBI_FWFT_GLOBAL_PLATFORM_END = 0xffffffff, +}; + +#define SBI_FWFT_GLOBAL_FEATURE_BIT (1 << 31) +#define SBI_FWFT_PLATFORM_FEATURE_BIT (1 << 30) + +#define SBI_FWFT_SET_FLAG_LOCK (1 << 0) + /* SBI spec version fields */ #define SBI_SPEC_VERSION_DEFAULT 0x1 #define SBI_SPEC_VERSION_MAJOR_SHIFT 24